Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation

Abstract

Adders are used in arithmetic and logic units (ALUs) as a key building block and many blocks of microprocessor chips critical path adders occupy an important place. Hence reducing power, area and increasing the speed of adders is significantly important. This paper proposes a modified structure of Carry Skip Adder (CSKA) with reduction in consumption of power and area without affecting the speed when compared with the conventional adder strctures. In order to get better effectiveness of the modified CSKA by including concatenation, incrementation schemes and variable latency for the proposed hybrid structure, which reduces the power utilized without affecting the operating speed of the adder. The modified structure in CSKA helps in improving the slack time which further reduces the voltage with the parallel structure. Experimental results show that the 32 bit implementation of proposed adder has a significant power reduction of 42.% and 38.3%, area reduction of 27% and 18.3% with respect to Conventional CSKA and CI CSKA adder with a little over ahead in delay. The proposed adder is used to implement a 5 tap FIR filter which shows a significant reduction in power consumption and area.

Keywords

• Carry Skip Adder
• Power Consumption
• FIR
• BEC

Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation

Abstract

Adders are used in processing units such as Arithmetic and Logic Units (ALUs) as an essential building block, and in many blocks of microprocessor chips critical path, adders occupy an important place. Hence reducing power, area and increasing the speed of adders are significantly important. This paper proposes a modified structure of Carry Skip Adder (CSKA) with a reduction in consumption of power and area without affecting the speed when compared with the conventional adder structures. In order to get better effectiveness of the modified CSKA by including concatenation, incrementation schemes, and variable latency for the proposed hybrid structure, which reduces the power utilized without affecting the operating speed of the adder. The modified structure in CSKA helps in improving the slack time, which further reduces the voltage with the parallel structure. Experimental results show that the 32-bit implementation of the proposed adder has a significant power reduction of 42% and 38.3%, area reduction of 27%, and 18.3% with respect to Conventional CSKA and CI CSKA adder with a little over ahead in delay. The proposed adder is used to implement a 5-tap FIR filter which shows a significant reduction in power consumption and area.

Keywords

• Carry Skip Adder
• Power Consumption
• FIR
• Binary to Excess Code convertor.

References

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