Year 2017, Volume 13 , Issue 1, Pages 1 - 9 2017-07-14

BZK.SAU.FPGA Mikro Bilgisayar Mimarisi için Assembler Tasarımı
Assembler Design for BZK.SAU.FPGA Micro Computer Architecture

Halit Öztekin [1] , Ali Gülbağ [2] , Feyzullah Temurtaş [3]


İşletim sistemleri ve assembler çalışmalarına olanak sağlamak amacı ile mikro bilgisayar mimarisinde bir bellek organizasyonu ve bellek haritası oluşturulmak gerekmektedir. BZK.SAU.FPGA mikro bilgisayar mimarisi assembler  komut kümesi 59 adet komuttan oluşmakta olup 6 farklı adresleme modunu kullanmaktadır. Bu çalışmada BZK.SAU.FPGA mikro bilgisayar mimarisi üzerine sıfırdan bir assembly dili nasıl tasarlanacağı gösterilmiştir. Assembler programı, kullanıcı kaynak programını makine koduna dönüştürürken Brute-force Search Algoritması’ nı kullanılmıştır.

It is necessary to constitute a memory organization and a memory map in the microcomputer architecture in order to allow operation systems and assembler to work. The BZK.SAU.FPGA microcomputer architecture assembler instruction set consists of 59 instructions and uses 6 different addressing modes. This work demonstrates how to design an assembly language from scratch on the BZK.SAU.FPGA microcomputer architecture. The assembler program uses the Brute-force Search Algorithm to convert the user source program to machine code.

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Journal Section Articles
Authors

Author: Halit Öztekin
Institution: BOZOK ÜNİVERSİTESİ
Country: Turkey


Author: Ali Gülbağ
Institution: SAKARYA ÜNİVERSİTESİ
Country: Turkey


Author: Feyzullah Temurtaş
Institution: BOZOK ÜNİVERSİTESİ

Dates

Application Date : June 12, 2017
Acceptance Date : June 12, 2017
Publication Date : July 14, 2017

Bibtex @research article { else320541, journal = {Electronic Letters on Science and Engineering}, issn = {1305-8614}, address = {Bozok University, Electrical and Electronics Engineering, Erdoğan Akdag Kampus, 66200, Yozgat, TURKEY.}, publisher = {Fevzullah TEMURTAŞ}, year = {2017}, volume = {13}, pages = {1 - 9}, doi = {}, title = {Assembler Design for BZK.SAU.FPGA Micro Computer Architecture}, key = {cite}, author = {Öztekin, Halit and Gülbağ, Ali and Temurtaş, Feyzullah} }
APA Öztekin, H , Gülbağ, A , Temurtaş, F . (2017). Assembler Design for BZK.SAU.FPGA Micro Computer Architecture . Electronic Letters on Science and Engineering , 13 (1) , 1-9 . Retrieved from https://dergipark.org.tr/en/pub/else/issue/30411/320541
MLA Öztekin, H , Gülbağ, A , Temurtaş, F . "Assembler Design for BZK.SAU.FPGA Micro Computer Architecture" . Electronic Letters on Science and Engineering 13 (2017 ): 1-9 <https://dergipark.org.tr/en/pub/else/issue/30411/320541>
Chicago Öztekin, H , Gülbağ, A , Temurtaş, F . "Assembler Design for BZK.SAU.FPGA Micro Computer Architecture". Electronic Letters on Science and Engineering 13 (2017 ): 1-9
RIS TY - JOUR T1 - Assembler Design for BZK.SAU.FPGA Micro Computer Architecture AU - Halit Öztekin , Ali Gülbağ , Feyzullah Temurtaş Y1 - 2017 PY - 2017 N1 - DO - T2 - Electronic Letters on Science and Engineering JF - Journal JO - JOR SP - 1 EP - 9 VL - 13 IS - 1 SN - 1305-8614- M3 - UR - Y2 - 2017 ER -
EndNote %0 Electronic Letters on Science and Engineering Assembler Design for BZK.SAU.FPGA Micro Computer Architecture %A Halit Öztekin , Ali Gülbağ , Feyzullah Temurtaş %T Assembler Design for BZK.SAU.FPGA Micro Computer Architecture %D 2017 %J Electronic Letters on Science and Engineering %P 1305-8614- %V 13 %N 1 %R %U
ISNAD Öztekin, Halit , Gülbağ, Ali , Temurtaş, Feyzullah . "Assembler Design for BZK.SAU.FPGA Micro Computer Architecture". Electronic Letters on Science and Engineering 13 / 1 (July 2017): 1-9 .
AMA Öztekin H , Gülbağ A , Temurtaş F . Assembler Design for BZK.SAU.FPGA Micro Computer Architecture. Electronic Letters on Science and Engineering. 2017; 13(1): 1-9.
Vancouver Öztekin H , Gülbağ A , Temurtaş F . Assembler Design for BZK.SAU.FPGA Micro Computer Architecture. Electronic Letters on Science and Engineering. 2017; 13(1): 1-9.