EFFICIENT HARDWARE ARCHITECTURE FOR SELECTIVE GRAY CODED BIT PLANE BASED LOW COMPLEXITY MOTION ESTIMATION

Abstract

In video compression, motion estimation (ME) is exploited to remove temporal redundancy. Computationally, ME is one of the most expensive parts of a video encoder. In this work, efficient and novel hardware architecture is proposed to implement selective Gray-coded bit-plane based motion estimation algorithm. Spiral search algorithm is employed as search scheme in the novel hardware architecture. Experimental results show that considerable amount of hardware resources are saved thanks to the proposed architecture compared to the recent works in the literature.

Keywords

• Video Coding,HEVC,Motion Estimation,FPGA,Hardware Architecture

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