Research Article
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Quantum dot Cellular Automata based Fault Tolerant Fingerprint Authentication Systems using Reversible Logic Gates

Year 2022, Volume: 35 Issue: 2, 586 - 604, 01.06.2022
https://doi.org/10.35378/gujs.797571

Abstract

The limits and difficulties looked by CMOS innovation in the nano system has prompted the exploration of other potential advancements which can work with same functionalities anyway with lower power scattering and higher speed. One such technology is Quantum dot Cellular Automata (QCA). In this paper, QCA is explored to design the authentication system. This paper first presents the basic operating principle of a Fingerprint Authentication System (FAS) followed by fault tolerance analysis of four efficient XOR gate designs in the literature. The XOR gate is then used in the proposed four fault tolerant designs of reversible FAS in QCA, which are based on different reversible gates. Based on the evaluation of different performance parameters, it is seen that the proposed FAS designs are cost efficient and achieve improvement up to 59.46% in terms of number of cells, 67.16% improvement in cell area, 67.14% improvement in total area, 66.67% improvement in latency and 90.51% improvement in terms of circuit cost from the existing design Furthermore, the energy dissipation examination of the proposed designs is also additionally introduced. Subsequently, the proposed designs can be effectively used in biometric applications demanding ultra-low power consumption, higher operating speed and minimal area utilization.

Project Number

CRS 1-5736612144

Thanks

The authors would like to thank National Project Implementation Unit (NPIU), a unit of Ministry of Education, Government of India and The World Bank, for providing financial assistance to carry out this research under TEQIP-III Collaborative Research Scheme (CRS) with sanction number: 1-5736612144.

References

  • [1] Lent, C. S., Tougaw, P., Porod, W. and Bernstein, G. H., "Quantum cellular automata," Nanotechnology, 4(1): 49, (1993).
  • [2] Smith, C. G., "Computation without current," Science, 284(5412): 274-274, (1999).
  • [3] Bilal, B., Ahmed, S. and Kakkar, V., "Quantum Dot Cellular Automata: A New Paradigm for Digital Design," International Journal of Nanoelectronics and Materials, 11(1): 87-98, (2018).
  • [4] Bilal, B., Ahmed, S., and Kakkar, V., "Modular adder designs using optimal reversible and fault tolerant gates in field-coupled QCA nanocomputing," International Journal of Theoretical Physics, 57(5): 1356-1375, (2018).
  • [5] Ahmad, F., Ahmed, S., Kakkar, V., Bhat, G. M., Bahar, A. N. and Wani, S., "Modular Design of Ultra-Efficient Reversible Full Adder-Subtractor in QCA with Power Dissipation Analysis," International Journal of Theoretical Physics, 57 (9): 2863-2880, (2018).
  • [6] Bilal, B., Ahmed, S. and Kakkar, V., "Multifunction reversbile logic gate: Logic synthesis and design implementation in QCA," IEEE International Conference on Computing, Communication and Automation (ICCCA), Greater Noida, India, 1385-1390, (2017).
  • [7] Nafees, N., Manzoor, I., Baba, M. I., Bhat, S. M., Puri, V. and Ahmed, S., "Modeling and Logic Synthesis of Multifunctional and Universal 3× 3 Reversible Gate for Nanoscale Applications," In: Singh Tomar G., Chaudhari N., Barbosa J., Aghwariya M. (eds) International Conference on Intelligent Computing and Smart Communication, Algorithms for Intelligent Systems, Springer, Singapore, 1423-1431, (2019).
  • [8] Manzoor, I., Nafees, N., Baba, M. I., Bhat, S. M., Puri, V. and Ahmed, S., "Logic Design and Modeling of an Ultraefficient 3× 3 Reversible Gate for Nanoscale Applications," In: Singh Tomar G., Chaudhari N., Barbosa J., Aghwariya M. (eds) International Conference on Intelligent Computing and Smart Communication, Algorithms for Intelligent Systems, Springer, Singapore, 1433-1442, (2019).
  • [9] Bilal, B., Ahmed, S. and Kakkar, V., "Optimal realization of universality of peres gate using explicit interaction of cells in quantum dot cellular automata nanotechnology," International Journal of Intelligent Systems and Applications, 9(6): 75-84, (2017).
  • [10] Raj, M., Ahmed, S. and Gopalakrishnan, L. "Subtractor circuits using different wire crossing techniques in quantum-dot cellular automata," Journal of Nanophotonics, 14(2): 026007, (2020).
  • [11] Ahmed, S., Baba, M. I., Bhat, S. M., Manzoor, I., Nafees, N. and Ko, S.-B.., "Design of reversible universal and multifunctional gate-based 1-bit full adder and full subtractor in quantum-dot cellular automata nanocomputing," Journal of Nanophotonics, 14(3): 036002, (2020).
  • [12] Bhat, S. M. and Ahmed, S., "Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis," International Journal of Theoretical Physics, 58(12): 4042-4063, (2019).
  • [13] Roohi, A., Zand, R., Angizi, S. and DeMara, R. F., "A parity-preserving reversible QCA gate with self-checking cascadable resiliency," IEEE Transactions on Emerging Topics in Computing, 6(4): 450-459, (2016).
  • [14] Fredkin, E. and Toffoli, T., "Conservative logic," International Journal of Theoretical Physics, 21(3-4): 219-253, (1982).
  • [15] Ma, X., Huang, J., Metra, C. and Lombardi, F., "Reversible and testable circuits for molecular QCA design," In: Tehranipoor M. (eds), Emerging Nanotechnologies. Frontiers in Electronic Testing, vol 37, Springer, Boston, MA, 157-202, (2008).
  • [16] Sen, B., Saran, D., Saha, M. and Sikdar, B. K., "Synthesis of reversible universal logic around QCA with online testability," IEEE International Symposium on Electronic System Design, 236-241, (2011).
  • [17] Moharrami, E. and Navimipour, N. J., "Designing nanoscale counter using reversible gate based on quantum-dot cellular automata," International Journal of Theoretical Physics, 57(4): 1060-1081, (2018).
  • [18] Das, J. C. and De, D., "QCA based design of Polar encoder circuit for nano communication network," Nano Communication Networks, 18: 82-92, (2018).
  • [19] Agrawal, P., Sinha, S., Misra, N. K. and Wairya, S., "Design of Quantum Dot Cellular Automata Based Parity Generator and Checker with Minimum Clocks and Latency," International Journal of Modern Education and Computer Science, 8(8): 11-20, (2016).
  • [20] Bahar, A. N., Uddin, M. S., Abdullah-Al-Shafi, M., Bhuiyan, M. M. R. and Ahmed, K., "Designing efficient QCA even parity generator circuits with power dissipation analysis," Alexandria Engineering Journal, 57(4): 2475-2484, (2018).
  • [21] Das, J. C.¸ De, D. and Sadhu, T., "A novel low power nanoscale reversible decoder using quantum-dot cellular automata for nanocommunication," 3rd IEEE International Conference on Devices, Circuits and Systems (ICDCS), 220-224, (2016).
  • [22] R. Singh and Sharma, D. K., "Fault Tolerant Reversible Gate Based Sequential Quantum Dot Cellular Automata Circuits: Design and Contemplation," Journal of Nanoelectronics and Optoelectronics, 15(3): 331-344, (2020).
  • [23] Abutaleb, M., "Robust and efficient quantum-dot cellular automata synchronous counters," Microelectronics Journal, 61: 6-14, (2017).
  • [24] Divshali, M. N., Rezai, A. and Hamidpour, S. S. F., "Design of Novel Coplanar Counter Circuit in Quantum Dot Cellular Automata Technology," International Journal of Theoretical Physics, 58(8): 2677-2691, (2019).
  • [25] Jeon, J.-C., "Low-complexity QCA universal shift register design using multiplexer and D flip-flop based on electronic correlations," The Journal of Supercomputing, 76(8): 6438-6452, (2020).
  • [26] Sadhu, A., Das, K., De, D. and Kanjilal, M. R., "Area-Delay-Energy aware SRAM memory cell and M× N parallel read/write memory array design for quantum dot cellular automata," Microprocessors and Microsystems, 72: 102944, (2020).
  • [27] Fam, S. R. and Navimipour, N. J., "Design of a loop-based random access memory based on the nanoscale quantum dot cellular automata," Photonic Network Communications, 37(1): 120-130, (2019).
  • [28] Mubarakali, A., Ramakrishnan, J., Mavaluru, D., Elsir, A., Elsier, O. and Wakil, K., "A new efficient design for random access memory based on quantum dot cellular automata nanotechnology," Nano Communication Networks, 21: 100252, (2019).
  • [29] Heikalabad, S. R., Navin, A. H. and Hosseinzadeh, M., "Content addressable memory cell in quantum-dot cellular automata," Microelectronic Engineering, 163: 140-150, (2016).
  • [30] Amlani, I., Orlov, A. O., Toth, G., Bernstein, G. H., Lent, C. S. and Snider, G. L., "Digital logic gate using quantum-dot cellular automata," Science, 284(5412): 289-291, (1999).
  • [31] Niemier, M. T. and Kogge, P. M., "Logic in wire: using quantum dots to implement a microprocessor," 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No. 99EX357), 1211-1215, (1999).
  • [32] Frost, S. E., Rodrigues, A. F., Janiszewski, A. W., Rausch, R. T. and Kogge, P. M., "Memory in motion: A study of storage structures in QCA," First Workshop on Non-Silicon Computing, 1-8, (2002).
  • [33] Bilal, B., Ahmed, S. and Kakkar, V., "An insight into beyond CMOS next generation computing using quantum-dot cellular automata nanotechnology," International Journal of Engineering and Manufacturing, 8(1): 25-37, (2018).
  • [34] Roohi, A., DeMara, R. F. and Khoshavi, N., "Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder," Microelectronics Journal, 46(6): 531-542, (2015).
  • [35] Ahmed, S., Bhat, S. M. and Ko, S. B., "Design of reversible gate-based fingerprint authentication system in quantum-dot cellular automata for secure nanocomputing," In: Singh P. K., Singh Y., Kolekar, M. H., Kar, A. K., Chhabra J. K., Sen A. (eds) International Conference on Recent Innovations in Computing, Lecture Notes in Electrical Engineering, 701, Springer, Singapore, 729-740, (2020).
  • [36] Debnath, B., Das, J. C. and De, D., "Fingerprint authentication using QCA technology," IEEE Conference on Devices for Integrated Circuit (DevIC), 125-130, (2017).
  • [37] Majeed, A. H., Zainal, M. S. B., Alkaldy, E. and Nor, D. M., "Full Adder Circuit Design with Novel Lower Complexity XOR Gate in QCA Technology," Transactions on Electrical and Electronic Materials, 21: 198-207, (2020).
  • [38] Chabi, A. M., Roohi, A., DeMara, R. F., Angizi, S., Navi, K. and Khademolhosseini, H., "Cost-efficient QCA reversible combinational circuits based on a new reversible gate," 18th IEEE CSI International Symposium on Computer Architecture and Digital Systems (CADS), 1-6, (2015).
  • [39] Bahar, A. N., Waheed, S., Hossain, N. and Asaduzzaman, M., "A novel 3-input XOR function implementation in quantum dot-cellular automata with energy dissipation analysis," Alexandria Engineering Journal, 57(2): 729-738, (2018).
  • [40] Ahmed, S. and Naz, S. F “Design of quantum dot cellular automata based fault tolerant convolution encoders for secure nanocomputing,” International Journal of Quantum Information, 18(6): 2050032, (2020).
  • [41] Walus, K., Dysart, T. J., Jullien, G. A., Budiman, R. A., “QCADesigner: a rapid design & simulation tool for quantum-dot cellular automata,” IEEE Transaction on Nanotechnology, 3(1): 26-31, (2004).
  • [42] Feynman, R. P., "Quantum mechanical computers," Foundations of Physics, 16(6): 507-532, (1986).
  • [43] Nagamani, A., Jayashree, H. and Bhagyalakshmi, H., "Novel low power comparator design using reversible logic gates," Indian Journal of Computer Science and Engineering, 2(4): 566-574, (2011).
  • [44] Toffoli, T., "Reversible computing," International Colloquium on Automata, Languages and Programming, Springer, 632-644, (1980).
  • [45] Parhami, B., "Fault-tolerant reversible circuits," Fortieth IEEE Asilomar Conference on Signals, Systems and Computers, 1726-1729, (2006).
  • [46] Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S., "QCAPro-an error-power estimation tool for QCA circuit design," IEEE International Symposium of Circuits and Systems (ISCAS), 2377-2380, (2011).
  • [47] Srivastava, S., Sarkar, S. and Bhanja, S., "Estimation of upper bound of power dissipation in QCA circuits," IEEE Transactions on Nanotechnology, 8(1): 116-127, (2008).
  • [48] Timler, J. and Lent, C. S., "Power gain and dissipation in quantum-dot cellular automata," Journal of Applied Physics, 91(2): 823-831, (2002).
Year 2022, Volume: 35 Issue: 2, 586 - 604, 01.06.2022
https://doi.org/10.35378/gujs.797571

Abstract

Project Number

CRS 1-5736612144

References

  • [1] Lent, C. S., Tougaw, P., Porod, W. and Bernstein, G. H., "Quantum cellular automata," Nanotechnology, 4(1): 49, (1993).
  • [2] Smith, C. G., "Computation without current," Science, 284(5412): 274-274, (1999).
  • [3] Bilal, B., Ahmed, S. and Kakkar, V., "Quantum Dot Cellular Automata: A New Paradigm for Digital Design," International Journal of Nanoelectronics and Materials, 11(1): 87-98, (2018).
  • [4] Bilal, B., Ahmed, S., and Kakkar, V., "Modular adder designs using optimal reversible and fault tolerant gates in field-coupled QCA nanocomputing," International Journal of Theoretical Physics, 57(5): 1356-1375, (2018).
  • [5] Ahmad, F., Ahmed, S., Kakkar, V., Bhat, G. M., Bahar, A. N. and Wani, S., "Modular Design of Ultra-Efficient Reversible Full Adder-Subtractor in QCA with Power Dissipation Analysis," International Journal of Theoretical Physics, 57 (9): 2863-2880, (2018).
  • [6] Bilal, B., Ahmed, S. and Kakkar, V., "Multifunction reversbile logic gate: Logic synthesis and design implementation in QCA," IEEE International Conference on Computing, Communication and Automation (ICCCA), Greater Noida, India, 1385-1390, (2017).
  • [7] Nafees, N., Manzoor, I., Baba, M. I., Bhat, S. M., Puri, V. and Ahmed, S., "Modeling and Logic Synthesis of Multifunctional and Universal 3× 3 Reversible Gate for Nanoscale Applications," In: Singh Tomar G., Chaudhari N., Barbosa J., Aghwariya M. (eds) International Conference on Intelligent Computing and Smart Communication, Algorithms for Intelligent Systems, Springer, Singapore, 1423-1431, (2019).
  • [8] Manzoor, I., Nafees, N., Baba, M. I., Bhat, S. M., Puri, V. and Ahmed, S., "Logic Design and Modeling of an Ultraefficient 3× 3 Reversible Gate for Nanoscale Applications," In: Singh Tomar G., Chaudhari N., Barbosa J., Aghwariya M. (eds) International Conference on Intelligent Computing and Smart Communication, Algorithms for Intelligent Systems, Springer, Singapore, 1433-1442, (2019).
  • [9] Bilal, B., Ahmed, S. and Kakkar, V., "Optimal realization of universality of peres gate using explicit interaction of cells in quantum dot cellular automata nanotechnology," International Journal of Intelligent Systems and Applications, 9(6): 75-84, (2017).
  • [10] Raj, M., Ahmed, S. and Gopalakrishnan, L. "Subtractor circuits using different wire crossing techniques in quantum-dot cellular automata," Journal of Nanophotonics, 14(2): 026007, (2020).
  • [11] Ahmed, S., Baba, M. I., Bhat, S. M., Manzoor, I., Nafees, N. and Ko, S.-B.., "Design of reversible universal and multifunctional gate-based 1-bit full adder and full subtractor in quantum-dot cellular automata nanocomputing," Journal of Nanophotonics, 14(3): 036002, (2020).
  • [12] Bhat, S. M. and Ahmed, S., "Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis," International Journal of Theoretical Physics, 58(12): 4042-4063, (2019).
  • [13] Roohi, A., Zand, R., Angizi, S. and DeMara, R. F., "A parity-preserving reversible QCA gate with self-checking cascadable resiliency," IEEE Transactions on Emerging Topics in Computing, 6(4): 450-459, (2016).
  • [14] Fredkin, E. and Toffoli, T., "Conservative logic," International Journal of Theoretical Physics, 21(3-4): 219-253, (1982).
  • [15] Ma, X., Huang, J., Metra, C. and Lombardi, F., "Reversible and testable circuits for molecular QCA design," In: Tehranipoor M. (eds), Emerging Nanotechnologies. Frontiers in Electronic Testing, vol 37, Springer, Boston, MA, 157-202, (2008).
  • [16] Sen, B., Saran, D., Saha, M. and Sikdar, B. K., "Synthesis of reversible universal logic around QCA with online testability," IEEE International Symposium on Electronic System Design, 236-241, (2011).
  • [17] Moharrami, E. and Navimipour, N. J., "Designing nanoscale counter using reversible gate based on quantum-dot cellular automata," International Journal of Theoretical Physics, 57(4): 1060-1081, (2018).
  • [18] Das, J. C. and De, D., "QCA based design of Polar encoder circuit for nano communication network," Nano Communication Networks, 18: 82-92, (2018).
  • [19] Agrawal, P., Sinha, S., Misra, N. K. and Wairya, S., "Design of Quantum Dot Cellular Automata Based Parity Generator and Checker with Minimum Clocks and Latency," International Journal of Modern Education and Computer Science, 8(8): 11-20, (2016).
  • [20] Bahar, A. N., Uddin, M. S., Abdullah-Al-Shafi, M., Bhuiyan, M. M. R. and Ahmed, K., "Designing efficient QCA even parity generator circuits with power dissipation analysis," Alexandria Engineering Journal, 57(4): 2475-2484, (2018).
  • [21] Das, J. C.¸ De, D. and Sadhu, T., "A novel low power nanoscale reversible decoder using quantum-dot cellular automata for nanocommunication," 3rd IEEE International Conference on Devices, Circuits and Systems (ICDCS), 220-224, (2016).
  • [22] R. Singh and Sharma, D. K., "Fault Tolerant Reversible Gate Based Sequential Quantum Dot Cellular Automata Circuits: Design and Contemplation," Journal of Nanoelectronics and Optoelectronics, 15(3): 331-344, (2020).
  • [23] Abutaleb, M., "Robust and efficient quantum-dot cellular automata synchronous counters," Microelectronics Journal, 61: 6-14, (2017).
  • [24] Divshali, M. N., Rezai, A. and Hamidpour, S. S. F., "Design of Novel Coplanar Counter Circuit in Quantum Dot Cellular Automata Technology," International Journal of Theoretical Physics, 58(8): 2677-2691, (2019).
  • [25] Jeon, J.-C., "Low-complexity QCA universal shift register design using multiplexer and D flip-flop based on electronic correlations," The Journal of Supercomputing, 76(8): 6438-6452, (2020).
  • [26] Sadhu, A., Das, K., De, D. and Kanjilal, M. R., "Area-Delay-Energy aware SRAM memory cell and M× N parallel read/write memory array design for quantum dot cellular automata," Microprocessors and Microsystems, 72: 102944, (2020).
  • [27] Fam, S. R. and Navimipour, N. J., "Design of a loop-based random access memory based on the nanoscale quantum dot cellular automata," Photonic Network Communications, 37(1): 120-130, (2019).
  • [28] Mubarakali, A., Ramakrishnan, J., Mavaluru, D., Elsir, A., Elsier, O. and Wakil, K., "A new efficient design for random access memory based on quantum dot cellular automata nanotechnology," Nano Communication Networks, 21: 100252, (2019).
  • [29] Heikalabad, S. R., Navin, A. H. and Hosseinzadeh, M., "Content addressable memory cell in quantum-dot cellular automata," Microelectronic Engineering, 163: 140-150, (2016).
  • [30] Amlani, I., Orlov, A. O., Toth, G., Bernstein, G. H., Lent, C. S. and Snider, G. L., "Digital logic gate using quantum-dot cellular automata," Science, 284(5412): 289-291, (1999).
  • [31] Niemier, M. T. and Kogge, P. M., "Logic in wire: using quantum dots to implement a microprocessor," 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No. 99EX357), 1211-1215, (1999).
  • [32] Frost, S. E., Rodrigues, A. F., Janiszewski, A. W., Rausch, R. T. and Kogge, P. M., "Memory in motion: A study of storage structures in QCA," First Workshop on Non-Silicon Computing, 1-8, (2002).
  • [33] Bilal, B., Ahmed, S. and Kakkar, V., "An insight into beyond CMOS next generation computing using quantum-dot cellular automata nanotechnology," International Journal of Engineering and Manufacturing, 8(1): 25-37, (2018).
  • [34] Roohi, A., DeMara, R. F. and Khoshavi, N., "Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder," Microelectronics Journal, 46(6): 531-542, (2015).
  • [35] Ahmed, S., Bhat, S. M. and Ko, S. B., "Design of reversible gate-based fingerprint authentication system in quantum-dot cellular automata for secure nanocomputing," In: Singh P. K., Singh Y., Kolekar, M. H., Kar, A. K., Chhabra J. K., Sen A. (eds) International Conference on Recent Innovations in Computing, Lecture Notes in Electrical Engineering, 701, Springer, Singapore, 729-740, (2020).
  • [36] Debnath, B., Das, J. C. and De, D., "Fingerprint authentication using QCA technology," IEEE Conference on Devices for Integrated Circuit (DevIC), 125-130, (2017).
  • [37] Majeed, A. H., Zainal, M. S. B., Alkaldy, E. and Nor, D. M., "Full Adder Circuit Design with Novel Lower Complexity XOR Gate in QCA Technology," Transactions on Electrical and Electronic Materials, 21: 198-207, (2020).
  • [38] Chabi, A. M., Roohi, A., DeMara, R. F., Angizi, S., Navi, K. and Khademolhosseini, H., "Cost-efficient QCA reversible combinational circuits based on a new reversible gate," 18th IEEE CSI International Symposium on Computer Architecture and Digital Systems (CADS), 1-6, (2015).
  • [39] Bahar, A. N., Waheed, S., Hossain, N. and Asaduzzaman, M., "A novel 3-input XOR function implementation in quantum dot-cellular automata with energy dissipation analysis," Alexandria Engineering Journal, 57(2): 729-738, (2018).
  • [40] Ahmed, S. and Naz, S. F “Design of quantum dot cellular automata based fault tolerant convolution encoders for secure nanocomputing,” International Journal of Quantum Information, 18(6): 2050032, (2020).
  • [41] Walus, K., Dysart, T. J., Jullien, G. A., Budiman, R. A., “QCADesigner: a rapid design & simulation tool for quantum-dot cellular automata,” IEEE Transaction on Nanotechnology, 3(1): 26-31, (2004).
  • [42] Feynman, R. P., "Quantum mechanical computers," Foundations of Physics, 16(6): 507-532, (1986).
  • [43] Nagamani, A., Jayashree, H. and Bhagyalakshmi, H., "Novel low power comparator design using reversible logic gates," Indian Journal of Computer Science and Engineering, 2(4): 566-574, (2011).
  • [44] Toffoli, T., "Reversible computing," International Colloquium on Automata, Languages and Programming, Springer, 632-644, (1980).
  • [45] Parhami, B., "Fault-tolerant reversible circuits," Fortieth IEEE Asilomar Conference on Signals, Systems and Computers, 1726-1729, (2006).
  • [46] Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S., "QCAPro-an error-power estimation tool for QCA circuit design," IEEE International Symposium of Circuits and Systems (ISCAS), 2377-2380, (2011).
  • [47] Srivastava, S., Sarkar, S. and Bhanja, S., "Estimation of upper bound of power dissipation in QCA circuits," IEEE Transactions on Nanotechnology, 8(1): 116-127, (2008).
  • [48] Timler, J. and Lent, C. S., "Power gain and dissipation in quantum-dot cellular automata," Journal of Applied Physics, 91(2): 823-831, (2002).
There are 48 citations in total.

Details

Primary Language English
Subjects Engineering
Journal Section Electrical & Electronics Engineering
Authors

Suhaib Ahmed 0000-0003-3496-8856

Syed Naz This is me 0000-0001-5651-4594

Sparsh Sharma This is me 0000-0001-8092-1683

Project Number CRS 1-5736612144
Publication Date June 1, 2022
Published in Issue Year 2022 Volume: 35 Issue: 2

Cite

APA Ahmed, S., Naz, S., & Sharma, S. (2022). Quantum dot Cellular Automata based Fault Tolerant Fingerprint Authentication Systems using Reversible Logic Gates. Gazi University Journal of Science, 35(2), 586-604. https://doi.org/10.35378/gujs.797571
AMA Ahmed S, Naz S, Sharma S. Quantum dot Cellular Automata based Fault Tolerant Fingerprint Authentication Systems using Reversible Logic Gates. Gazi University Journal of Science. June 2022;35(2):586-604. doi:10.35378/gujs.797571
Chicago Ahmed, Suhaib, Syed Naz, and Sparsh Sharma. “Quantum Dot Cellular Automata Based Fault Tolerant Fingerprint Authentication Systems Using Reversible Logic Gates”. Gazi University Journal of Science 35, no. 2 (June 2022): 586-604. https://doi.org/10.35378/gujs.797571.
EndNote Ahmed S, Naz S, Sharma S (June 1, 2022) Quantum dot Cellular Automata based Fault Tolerant Fingerprint Authentication Systems using Reversible Logic Gates. Gazi University Journal of Science 35 2 586–604.
IEEE S. Ahmed, S. Naz, and S. Sharma, “Quantum dot Cellular Automata based Fault Tolerant Fingerprint Authentication Systems using Reversible Logic Gates”, Gazi University Journal of Science, vol. 35, no. 2, pp. 586–604, 2022, doi: 10.35378/gujs.797571.
ISNAD Ahmed, Suhaib et al. “Quantum Dot Cellular Automata Based Fault Tolerant Fingerprint Authentication Systems Using Reversible Logic Gates”. Gazi University Journal of Science 35/2 (June 2022), 586-604. https://doi.org/10.35378/gujs.797571.
JAMA Ahmed S, Naz S, Sharma S. Quantum dot Cellular Automata based Fault Tolerant Fingerprint Authentication Systems using Reversible Logic Gates. Gazi University Journal of Science. 2022;35:586–604.
MLA Ahmed, Suhaib et al. “Quantum Dot Cellular Automata Based Fault Tolerant Fingerprint Authentication Systems Using Reversible Logic Gates”. Gazi University Journal of Science, vol. 35, no. 2, 2022, pp. 586-04, doi:10.35378/gujs.797571.
Vancouver Ahmed S, Naz S, Sharma S. Quantum dot Cellular Automata based Fault Tolerant Fingerprint Authentication Systems using Reversible Logic Gates. Gazi University Journal of Science. 2022;35(2):586-604.