A PERFORMANCE ANALYSIS OF CLASSIFIED BINARY ADDER ARCHITECTURES AND THE VHDL SIMULATIONS

Abstract

In this paper, the  four  binary  adder architectures belong to a different adder class are studied  and  compared with each other  to analyse their performances.  Comparisons include the unit-gate models for area and  delay. As the performance measure, the product of  the area and the delay is used.  By a VHDL simulator, the adder structures are simulated to verify the functional correctness and  to measure delay times

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