CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT

Abstract

This paper proposes a CMOS current-mode multi_input analog multiplier and divider circuit based on a new method. Exponential and logarithmic functions are employed to realize the circuit which is used in neural network and fuzzy integrated systems. The major advantages of this multiplier are ability of having multi_input signals, and low Total Harmonic Distortion (THD). The circuit is designed and simulated using MATLAB software and HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35μm standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 0.9% and a THD of 0.42% in 1MHz. Moreover, the maximum power consumption of the circuit is found to be 0.89mW.

Keywords

• Multi_input Multiplier, Divider Circuit, Low THD, High Linear.

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20. Ali Naderi Saatlo was born in Urmia, Iran, in 1982. He received his B.Sc. degree in Communication Engineering from Urmia Azad University, Urmia, Iran, in 2005, and M.Sc. degree in Electrical Engineering from Urmia University in 2008. He is currently PhD student of Electrical and Electronics Engineering in Institute of Science and Technology of Istanbul Technical University, Istanbul, Turkey. Since 2011, he has been a faculty member of electrical engineering department of Urmia Azad University, Urmia, Iran. His research interests are analog and digital integrated circuit design for fuzzy applications, fuzzy sets and systems, high performance analog circuits, and digital signal processing. He is the author or coauthor of more than 20 peer-reviewed papers in international and national journals and conference proceedings.