A NOVEL REVERSIBLE FAULT TOLERANT MICROPROCESSOR DESIGN IN AMS 0.35UM PROCESS

Abstract

In this study, reversible circuits are revisited to achieve extreme soft-defect awareness in classical CMOS circuits. Defect models in the literature are reviewed and defect scattering is analyzed. A reversible 8-bit full adder is designed in 12-bit block code domain. As a proof of concept, a pair of reversible ALUs are embedded into a microprocessor with block-code encoded data-path. The design is simulated in ams 0.35um process and a layout is obtained for tapeout.

Keywords

• Reversible Computing,Fault Tolerance,Microprocessor

References

1. [1] Binder D., Smith, E.C. and Holman, A.B., 1975. “Satellite anomalies from galactic cosmic rays”, IEEE Trans. Nucl. Sci., vol. NS-22, no. 6, pp. 2675–2680.
2. [2] May, T.C. and Woods, M.H., 1978. “A new physical mechanism for soft errors in dynamic memories”, in Proc. Int’l Rel. Phys. Symp. (IRPS), pp. 33–40.
3. [3] Nicolaidis, M. ed., 2010. Soft errors in modern electronic systems (Vol. 41). Springer Science & Business Media.
4. [4] Toffoli, T., 1980. J. W. de Bakker and J. van Leeuwen, ed. "Reversible computing". Automata, Languages and Programming, Seventh Colloquium. Springer Verlag, Noordwijkerhout, Netherland.
5. [5] Maslov, D., Dueck, G. W., and Miller, D.M., “Toffoli Network Synthesis with Templates. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, June 2005
6. [6] Brown, J., 2000, The Quest for the Quantum Computer, Touchstone, New York.
7. [7] Benioff, P., 1980. The computer as a physical system: A microscopic quantum mechanical Hamiltonian model of computers as represented by Turing machines. Journal of Statistical Physics, 22(5), pp.563-591
8. [8] Beckman, D., Chari, A.N., Devabhaktuni, S., and Preskill, J., 1996. Efficient networks for quantum factoring. Physical Review A, 54(2), p.1034.

9. [9] Moore, G.E., 1965. Cramming more components onto integrated circuits, Electronics Magazine. p. 4.
10. [10] Miller, D.M., Maslov, D., and Dueck, G.W., 2003, June. A transformation based algorithm for reversible logic synthesis. In Proceedings of the 40th annual Design Automation Conference (pp. 318-323). ACM
11. [11] Wille, R. and Drechsler, R., 2009, July. BDD-based synthesis of reversible logic for large functions. In Proceedings of the 46th Annual Design Automation Conference (pp. 270-275). ACM.
12. [12] Miller, D.M. and Thornton, M.A., 2006, May. QMDD: A decision diagram structure for reversible and quantum circuits. In Multiple-Valued Logic, 2006. ISMVL 2006. 36th International Symposium on (pp. 30-30). IEEE.
13. [13] Soeken, M., Wille, R., Hilken, C., Przigoda, N., and Drechsler, R., 2012, January. Synthesis of reversible circuits with minimal lines for large functions. In Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific (pp. 85-92). IEEE.
14. [14] Bennett, C.H., 2003. Notes on Landauer's principle, reversible computation, and Maxwell's Demon. Studies In History and Philosophy of Science Part B: Studies In History and Philosophy of Modern Physics, 34(3), pp.501-510.
15. [15] Landauer, R., 1961. Irreversibility and heat generation in the computing process. IBM journal of research and development, 5(3), pp.183-191.
16. [16] Willingham, D.J. and Kale, I., 2008. Using positive feedback adiabatic logic to implement reversible Toffoli gates.
17. [17] Thomsen, M.K., 2012. Design of reversible logic circuits using standard cells: Standard cells and functional programming. Department of Computer Science, University of Copenhagen.
18. [18] Burignat, S., Thomsen, M.K., Klimczak, M., Olczak, M., and De Vos, A., 2011. Interfacing reversible pass-transistor CMOS chips with conventional restoring CMOS circuits. InReversible Computation (pp. 112-122). Springer Berlin Heidelberg.
19. [19] Susam, O. and Altun, M., 2016. Fast Synthesis of Reversible Circuits using a Sorting Algorithm and Optimization. Journal of Multiple-Valued Logic and Soft Computing, accepted for publication.
20. [20] Wootters, W., Zurek, W., 1982. "A Single Quantum Cannot be Cloned". Nature 299: 802–803.
21. [21] Wille, R., Große, D., Teuber, L., Dueck, G.W., and Drechsler, R., 2008, May. RevLib: An online resource for reversible functions and reversible circuits. In Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on (pp. 220-225). IEEE.
22. [22] Parhami, B., 2006, October. Fault-tolerant reversible circuits. In Signals, Systems and Computers, 2006. ACSSC'06. Fortieth Asilomar Conference on (pp. 1726-1729). IEEE.
23. [23] Boykin, P.O. and Roychowdhury, V.P., 2005, June. Reversible fault-tolerant logic. In Dependable Systems and Networks, 2005. DSN 2005. Proceedings. International Conference on (pp. 444-453). IEEE.
24. [24] Przigoda, N., Dueck, G., Wille, R. and Drechsler, R., 2016. Fault Detection in Parity Preserving Reversible Circuits.
25. [25] DiVincenzo, D.P. and Shor, P.W., 1996. Fault-tolerant error correction with efficient quantum codes. Physical review letters, 77(15), p.3260.
26. [26] Van Rentergem, Y. and De Vos, A., 2005. Optimal design of a reversible full adder. International Journal of Unconventional Computing, 1(4), p.339.