A NOVEL REVERSIBLE FAULT TOLERANT MICROPROCESSOR DESIGN IN AMS 0.35UM PROCESS

Yıl 2017, Cilt: 17 Sayı: 1, 3169 - 3178, 27.03.2017

M. Hüsrev Cılasun Mustafa Altun

Öz

In this study, reversible circuits are revisited
to achieve extreme soft-defect awareness in classical CMOS circuits. Defect
models in the literature are reviewed and defect scattering is analyzed. A
reversible 8-bit full adder is designed in 12-bit block code domain. As a proof
of concept, a pair of reversible ALUs are embedded into a microprocessor with
block-code encoded data-path. The design is simulated in ams 0.35um process and
a layout is obtained for tapeout.

Anahtar Kelimeler

Reversible Computing , Fault Tolerance , Microprocessor

Kaynakça

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