Research Article
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Year 2025, Volume: 13 Issue: 3, 965 - 974, 01.09.2025
https://doi.org/10.36306/konjes.1632887

Abstract

References

  • J. Remple and I. Galton, "The effects of inter-symbol interference in dynamic element matching DACs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 1, pp. 14–23, Jan. 2017.
  • A. Y. Hassan, "Enhancing signal detection in frequency selective channels by exploiting time diversity in inter-symbol interference signal," Wireless Pers. Commun., vol. 106, pp. 1373–1395, 2019.
  • S. Kim and I. Galton, "Adaptive cancellation of inter-symbol interference in high-speed continuous-time DACs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 70, no. 11, pp. 4309–4322, Nov. 2023, doi: 10.1109/TCSI.2023.3301714.
  • M. Hosney, H. A. I. Selmy, A. Srivastava, and K. M. F. Elsayed, "Interference mitigation using angular diversity receiver with efficient channel estimation in MIMO VLC," IEEE Access, vol. 8, pp. 54060–54073, 2020.
  • J. Liu and X. Lin, "Equalization in high-speed communication systems," IEEE Circuits Syst. Mag., vol. 4, no. 2, pp. 4–17, 2004.
  • N. Shwetha and M. Priyatham, "Performance analysis of self-adaptive equalizers using EPLMS algorithm," in Proc. 2020 4th Int. Conf. I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC), Palladam, India, 2020, pp. 872–876.
  • F. T. Gebreyohannes, A. Frappé, and A. Kaiser, "Semi-digital FIR DAC for low power single carrier IEEE 802.11ad 60 GHz transmitter," in Proc. IEEE 13th Int. New Circuits Syst. Conf. (NEWCAS), 2015, pp. 1–4.
  • M. R. Sadeghifar, H. Bengtsson, J. J. Wikner, and O. Gustafsson, "Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC," Integration, vol. 66, pp. 128–134, 2019.
  • M. R. Sadeghifar, O. Gustafsson, and J. J. Wikner, "Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics," Analog Integr. Circ. Signal Process., 2018.
  • E. OhAnnaidh, S. Rouat, S. Verhaeren, S. L. Tual, and C. Garnier, "A 3.2 GHz sample-rate 800 MHz bandwidth highly reconfigurable analog FIR filter in 45 nm CMOS," in Proc. IEEE ISSCC, Analog Techniques, San Francisco, CA, USA, Feb. 2010.
  • V. Srinivasan, G. Rosen, and P. Hasler, "Low-power realization of FIR filters using current-mode analog design techniques," in Proc. ACSSC, 2004, vol. 2, pp. 2223–2227.
  • G. Xu and J. Yuan, "A CMOS analog FIR filter with low phase distortion," in Proc. ESSCIRC, 2002, pp. 747–750. A. Petraglia and S. K. Mitra, "Effects of coefficient inaccuracy in switched-capacitor transversal filters," IEEE Trans. Circuits Syst., vol. 38, no. 9, pp. 977–983, Sep. 1991.
  • P. Liu, Y. B. Kim, and Y. J. Lee, "An accurate timing model for nano CMOS circuit considering statistical process variation," in Proc. IEEE Int. SoC Design Conf., Seoul, South Korea, Oct. 2007, pp. 269–327.
  • S. Patil, S. G. Rao, Y. Chen, and Y. Tsividis, "Signal encoding and processing in continuous time using a cascade of digital delays," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 3, pp. 1017–1030, Mar. 2019.
  • N. Akyuz, "Effects of random delay errors in transversal filters," M.S. thesis, Univ. Texas Dallas, Dallas, TX, USA, 2011.
  • M. T. Ozgun and M. Torlak, "Effects of random delay errors in continuous-time semi-digital transversal filters," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 1, pp. 183–190, 2014.
  • G. Cauwenberghs and G. C. Temes, “Adaptive digital correction of analog errors in MASH ADCs. I. Off line and blind on line calibration,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 7, pp. 621–628, Jul. 2000, doi: 10.1109/82.850421.
  • A. Mandal and R. Mishra, “Digital equalization for cancellation of noise like interferences in adaptive spatial filtering,” Circuits Syst. Signal Process., vol. 36, pp. 675–702, 2017.
  • A. G. K. C. Lim, V. Sreeram, and G. Q. Wang, “Digital compensation in IQ modulators using adaptive FIR filters,” IEEE Trans. Veh. Technol., vol. 53, no. 6, pp. 1809–1817, Nov. 2004, doi: 10.1109/TVT.2004.836934.
  • K. K. Shyu and C. Y. Chang, “Modified FIR filter with phase compensation technique to feedforward active noise controller design,” IEEE Trans. Ind. Electron., vol. 47, no. 2, pp. 444–453, Apr. 2000, doi: 10.1109/41.836361.
  • G. Fan, Y. Huang, Y. Su, J. Li, and G. Sun, “A reduced bias delay lock loop for adaptive filters,” Adv. Space Res., vol. 59, no. 1, pp. 230–235, Jan. 2017.
  • S. Moon, K. Shin, and D. Jeon, “Enhancing reliability of analog neural network processors,” IEEE Trans. Very Large Scale Integr. Syst., vol. 27, no. 6, pp. 1455–1459, Jun. 2019, doi: 10.1109/TVLSI.2019.2893256.
  • R. Rafieisangari and N. Shiri, “A neural network based error correction in the first stage residue of pipelined analog to digital converters,” Int. J. Circuit Theory Appl., vol. 52, no. 12, pp. 6001–6027, Dec. 2024, doi: 10.1002/cta.4076.
  • N. Nambath et al., “All analog adaptive equalizer for coherent data center interconnects,” J. Lightwave Technol., vol. 38, no. 21, pp. 5867–5874, Nov. 2020, doi: 10.1109/JLT.2020.2987140.
  • P. Teymouri, M. R. Mosavi, and M. Moazedi, “Delay spoofing reduction in GPS navigation system based on Time and Transform Domain adaptive filtering,” Iranian Journal of Electrical and Electronic Engineering, vol. 14, no. 3, pp. 222–235, Sep. 2018, doi: 10.22068/IJEEE.14.3.222.
  • Y. Sun, J. Wu, Y. Li, and D. J. Moss, “Comparison of microcomb based radio frequency photonic transversal signal processors implemented with discrete components versus integrated chips,” Micromachines, vol. 14, no. 9, p. 1794, Sep. 2023, doi: 10.3390/mi14091794.
  • K. Avcı and A. Nacaroğlu, “Computation of noise in switched capacitor networks due to the random fluctuation of the switching instants,” in Proc. 1st Int. Conf. Informatics (ICI), Çeşme, Turkey, Sep. 2004, pp. 1–4.
  • K. Avcı and A. Nacaroğlu, “Analysis of the effect of periodic fluctuation of switching instants on the transfer characteristics of switched capacitor networks,” Int. J. Circuit Theory Appl., vol. 22, pp. 15–24, 1994.

DESIGN OF ADAPTIVE TRANSVERSAL FILTER UNDER RANDOM DELAY VARIATIONS

Year 2025, Volume: 13 Issue: 3, 965 - 974, 01.09.2025
https://doi.org/10.36306/konjes.1632887

Abstract

Transversal filters consist of fundamental circuit elements such as adders, multipliers, and unit delay elements. The performance of these filters is affected by inaccuracies in these components, particularly limited precision in delay elements, which becomes significant in high-frequency semi-digital transversal filters. This letter proposes a cascaded delay element structure to mitigate precision errors. The main delay element is complemented by smaller cascaded delay elements, refining overall delay precision. To further enhance accuracy, a neural network (NN)-based adaptation scheme dynamically fine-tunes delay adjustments in real time. The proposed two-layer NN takes inputs from both the primary and cascaded delay elements and generates an optimized output for the next delay stage. The input layer neurons are randomly initialized, while the NN weights are iteratively updated using gradient descent to minimize errors. The neural network weights are determined during an initial factory‑calibration stage and remain fixed during all subsequent filter operation. Simulation results demonstrate that the cascaded delay structure, combined with NN adaptation, significantly reduces precision errors, enhancing semi-digital transversal filter performance for high-speed signal processing applications.

References

  • J. Remple and I. Galton, "The effects of inter-symbol interference in dynamic element matching DACs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 1, pp. 14–23, Jan. 2017.
  • A. Y. Hassan, "Enhancing signal detection in frequency selective channels by exploiting time diversity in inter-symbol interference signal," Wireless Pers. Commun., vol. 106, pp. 1373–1395, 2019.
  • S. Kim and I. Galton, "Adaptive cancellation of inter-symbol interference in high-speed continuous-time DACs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 70, no. 11, pp. 4309–4322, Nov. 2023, doi: 10.1109/TCSI.2023.3301714.
  • M. Hosney, H. A. I. Selmy, A. Srivastava, and K. M. F. Elsayed, "Interference mitigation using angular diversity receiver with efficient channel estimation in MIMO VLC," IEEE Access, vol. 8, pp. 54060–54073, 2020.
  • J. Liu and X. Lin, "Equalization in high-speed communication systems," IEEE Circuits Syst. Mag., vol. 4, no. 2, pp. 4–17, 2004.
  • N. Shwetha and M. Priyatham, "Performance analysis of self-adaptive equalizers using EPLMS algorithm," in Proc. 2020 4th Int. Conf. I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC), Palladam, India, 2020, pp. 872–876.
  • F. T. Gebreyohannes, A. Frappé, and A. Kaiser, "Semi-digital FIR DAC for low power single carrier IEEE 802.11ad 60 GHz transmitter," in Proc. IEEE 13th Int. New Circuits Syst. Conf. (NEWCAS), 2015, pp. 1–4.
  • M. R. Sadeghifar, H. Bengtsson, J. J. Wikner, and O. Gustafsson, "Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC," Integration, vol. 66, pp. 128–134, 2019.
  • M. R. Sadeghifar, O. Gustafsson, and J. J. Wikner, "Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics," Analog Integr. Circ. Signal Process., 2018.
  • E. OhAnnaidh, S. Rouat, S. Verhaeren, S. L. Tual, and C. Garnier, "A 3.2 GHz sample-rate 800 MHz bandwidth highly reconfigurable analog FIR filter in 45 nm CMOS," in Proc. IEEE ISSCC, Analog Techniques, San Francisco, CA, USA, Feb. 2010.
  • V. Srinivasan, G. Rosen, and P. Hasler, "Low-power realization of FIR filters using current-mode analog design techniques," in Proc. ACSSC, 2004, vol. 2, pp. 2223–2227.
  • G. Xu and J. Yuan, "A CMOS analog FIR filter with low phase distortion," in Proc. ESSCIRC, 2002, pp. 747–750. A. Petraglia and S. K. Mitra, "Effects of coefficient inaccuracy in switched-capacitor transversal filters," IEEE Trans. Circuits Syst., vol. 38, no. 9, pp. 977–983, Sep. 1991.
  • P. Liu, Y. B. Kim, and Y. J. Lee, "An accurate timing model for nano CMOS circuit considering statistical process variation," in Proc. IEEE Int. SoC Design Conf., Seoul, South Korea, Oct. 2007, pp. 269–327.
  • S. Patil, S. G. Rao, Y. Chen, and Y. Tsividis, "Signal encoding and processing in continuous time using a cascade of digital delays," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 3, pp. 1017–1030, Mar. 2019.
  • N. Akyuz, "Effects of random delay errors in transversal filters," M.S. thesis, Univ. Texas Dallas, Dallas, TX, USA, 2011.
  • M. T. Ozgun and M. Torlak, "Effects of random delay errors in continuous-time semi-digital transversal filters," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 1, pp. 183–190, 2014.
  • G. Cauwenberghs and G. C. Temes, “Adaptive digital correction of analog errors in MASH ADCs. I. Off line and blind on line calibration,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 7, pp. 621–628, Jul. 2000, doi: 10.1109/82.850421.
  • A. Mandal and R. Mishra, “Digital equalization for cancellation of noise like interferences in adaptive spatial filtering,” Circuits Syst. Signal Process., vol. 36, pp. 675–702, 2017.
  • A. G. K. C. Lim, V. Sreeram, and G. Q. Wang, “Digital compensation in IQ modulators using adaptive FIR filters,” IEEE Trans. Veh. Technol., vol. 53, no. 6, pp. 1809–1817, Nov. 2004, doi: 10.1109/TVT.2004.836934.
  • K. K. Shyu and C. Y. Chang, “Modified FIR filter with phase compensation technique to feedforward active noise controller design,” IEEE Trans. Ind. Electron., vol. 47, no. 2, pp. 444–453, Apr. 2000, doi: 10.1109/41.836361.
  • G. Fan, Y. Huang, Y. Su, J. Li, and G. Sun, “A reduced bias delay lock loop for adaptive filters,” Adv. Space Res., vol. 59, no. 1, pp. 230–235, Jan. 2017.
  • S. Moon, K. Shin, and D. Jeon, “Enhancing reliability of analog neural network processors,” IEEE Trans. Very Large Scale Integr. Syst., vol. 27, no. 6, pp. 1455–1459, Jun. 2019, doi: 10.1109/TVLSI.2019.2893256.
  • R. Rafieisangari and N. Shiri, “A neural network based error correction in the first stage residue of pipelined analog to digital converters,” Int. J. Circuit Theory Appl., vol. 52, no. 12, pp. 6001–6027, Dec. 2024, doi: 10.1002/cta.4076.
  • N. Nambath et al., “All analog adaptive equalizer for coherent data center interconnects,” J. Lightwave Technol., vol. 38, no. 21, pp. 5867–5874, Nov. 2020, doi: 10.1109/JLT.2020.2987140.
  • P. Teymouri, M. R. Mosavi, and M. Moazedi, “Delay spoofing reduction in GPS navigation system based on Time and Transform Domain adaptive filtering,” Iranian Journal of Electrical and Electronic Engineering, vol. 14, no. 3, pp. 222–235, Sep. 2018, doi: 10.22068/IJEEE.14.3.222.
  • Y. Sun, J. Wu, Y. Li, and D. J. Moss, “Comparison of microcomb based radio frequency photonic transversal signal processors implemented with discrete components versus integrated chips,” Micromachines, vol. 14, no. 9, p. 1794, Sep. 2023, doi: 10.3390/mi14091794.
  • K. Avcı and A. Nacaroğlu, “Computation of noise in switched capacitor networks due to the random fluctuation of the switching instants,” in Proc. 1st Int. Conf. Informatics (ICI), Çeşme, Turkey, Sep. 2004, pp. 1–4.
  • K. Avcı and A. Nacaroğlu, “Analysis of the effect of periodic fluctuation of switching instants on the transfer characteristics of switched capacitor networks,” Int. J. Circuit Theory Appl., vol. 22, pp. 15–24, 1994.
There are 28 citations in total.

Details

Primary Language English
Subjects Electronic Device and System Performance Evaluation, Testing and Simulation, Signal Processing
Journal Section Research Article
Authors

Nurbanu Güzey 0000-0002-6587-2489

Publication Date September 1, 2025
Submission Date February 4, 2025
Acceptance Date July 4, 2025
Published in Issue Year 2025 Volume: 13 Issue: 3

Cite

IEEE N. Güzey, “DESIGN OF ADAPTIVE TRANSVERSAL FILTER UNDER RANDOM DELAY VARIATIONS”, KONJES, vol. 13, no. 3, pp. 965–974, 2025, doi: 10.36306/konjes.1632887.