Implementation of Dormand-Prince based chaotic oscillator designs in different IQ-Math number standards on FPGA

Year 2019, , 859 - 868, 01.10.2019

İsmail Koyuncu , Halil İbrahim Şeker

https://doi.org/10.16984/saufenbilder.505497

Cited By: 4

Abstract

Chaos and chaotic systems, one of the most important work areas in
recent years, are used in areas such as cryptology and secure communication,
industrial control, artificial neural networks, random number generators and
image processing. The most basic structure used in these studies is a chaotic
oscillator design that produces a chaotic signal. Chaotic oscillators are
expressed by using differential equations. Numerical algorithms such as Euler,
Heun, fourth order Runge-Kutta-4 (RK4), fifth order RK5-Butcher and
Dormand-Prince are used for solving these differential equations. When the
current literature is searched, chaotic oscillator designs are found by Euler,
Heun, RK4 and RK5- Butcher method. However, FPGA-based chaotic oscillator
design studies have not been found using the Dormand-Prince method, which
produces more accurate solutions than other methods. In this work, self-excited
attractor chaotic
system was first designed in 16I-16Q, 14I-14Q, 12I-12Q, 10I_10Q, 8I-8Q IQ-Math number standards on FPGA using
Dormand-Prince numerical algorithm and encoded in VHDL language.
Xilinx ISE Design Tools were used to design the chaotic system. The
design was synthesized and tested for the Xilinx Virtex-6 FPGA chip. Using the
Xilinx ISE design tool, the chip statistics and maximum operating frequency
obtained after the "Route-Place" operation are presented. In future
work, safe communication and real random number generator applications can be
realized by using the Dormand-Prince based oscillator design presented in this
study.

Keywords

Dormand-Prince algorithm, FPGA, chaotic oscillator, VHDL

References

• [1] Tuna, M., Fidan, C.B., "A Study on the importance of chaotic oscillators based on FPGA for true random number generating (TRNG) and chaotic systems", Journal of the Faculty of Engineering and Architecture of Gazi University, 33(2), pp: 469-486, 2018.
• [2] Yılmaz D., Güler N.F., A Study on the Chaotic Time Series Analysis, Journal of the Faculty of Engineering and Architecture of Gazi University, 21 (4), 759-779, 2006.
• [3] Yassen, M. T., Chaos synchronization between two different chaotic systems using active control,” Chaos, Solitons & Fractals, 23(1): 131-140, 2005.
• [4] Park, J. H., and Kwon, O. M., “A novel criterion for delayed feedback control of time-delay chaotic systems”. Chaos, Solitons & Fractals, 23.2: 495-501, 2005.
• [5] Chen, G., Mao, Y., & Chui, C. K. "A symmetric image encryption scheme based on 3D chaotic cat maps", Chaos, Solitons & Fractals, 21(3), 749-761, 2004.
• [6] Pareek, Narendra K., Vinod, Patidar, and Krishan, K. Sud. "Image encryption using chaotic logistic map", Image and vision computing, 24: 9926-934, 2006.
• [7] Pehlivan, İ., Uyaroğlu, Y., Yalçın, M. A., & Ferikoğlu, A. “Sprott_94_A Kaotik Sisteminin Senkronizasyonu ve Bilgi Gizlemede Kullanılması,” Uluslararası Katılımlı Bilgi güvenliği ve Kriptoloji Konferansı, 2007.
• [8] Li, S. J., Mou, X. Q., & Cai, Y. L., “Pseudo-random bit generator based on couple chaotic systems and its application in stream-ciphers cryptography,” In Progress in Cryptology–INDOCRYPT 2001: Second International Conference on Cryptology, in India Chennai, India, December 16 C20, 2001 Proceedings pp. 316-329, 2001.
• [9] Alçın, M., “The Effect on Modelling Performance of Different Activation Functions for Feed Forward and Feedback Network Structures in Modeling of Chen Chaotic System,” International Journal of Scientific and Technological Research, ISSN 2422-8702 (Online), Vol 3, No.7, 2017.
• [10] Karunasinghe, Dulakshi SK, and Shie-Yui Liong., “Chaotic time series prediction with a global model: Artificial neural network,” Journal of Hydrology, 323.1-4: 92-105, 2006.
• [11] Lin, J. S., & Huang, S. M. “An FPGA-based brain-computer interface for wireless electric wheelchairs,” In Applied Mechanics and Materials, (Vol. 284, pp. 1616-1621). Trans Tech Publications. (2013).
• [12] dos Santos C.L., “Tuning of PID controller for an automatic regulator voltage system using chaotic optimization approach,” Chaos, Solitons & Fractals, 39(4): 1504-1514, 2009.
• [13] Lu, J., Xinghuo Y., and Guanrong C., “Generating chaotic attractors with multiple merged basins of attraction: A switching piecewise-linear control approach,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 50.2: 198-207, 2003.
• [14] Danger, J. L., Guilley, S., & Hoogvorst, P., “High speed true random number generator based on open loop structures in FPGAs,” Microelectronics journal, 40(11), 1650-1656, (2009).
• [15] Varchola, M., & Drutarovsky, M., “New high entropy element for FPGA based true random number generators,” In International Workshop on Cryptographic Hardware and Embedded Systems (pp. 351-365). Springer, Berlin, Heidelberg, 2010.
• [16] Dmitriev, A., Starkov, S., and Yemetz, S., “Chaotic communication using digital signal processors,” Nonlinear Theory and Applications, 3: 1093-1096, 2000.
• [17] Alçın, M., Tuna, M., Koyuncu, İ., “IQ-Math Based Designing of Fourth Order Runge-Kutta Algorithm on FPGA and Performance Analysis According to ANN Approximation,” International Journal of AdvancedResearch in Science Engineering and Technology, 5(8): 6523–6530, 2018.
• [18] Pehlivan, İ., Uyaroğlu, Y. ve Yoğun, M., “Chaotic oscillator design and realizations of the Rucklidge attractor and its synchronization and masking simulations,” Scientific Research and Essays, 5(16): 2210-2219, 2010.
• [19] Rajagopalan, S., Rethinam, S., Deepika, A. N., Priyadarshini, A., Jyothirmai, M., Rengarajan, A., Rajagopalan, Sundararaman, et al. “Design of boolean chaotic oscillator using CMOS technology for true random number generation,” Microelectronic Devices, Circuits and Systems (ICMDCS), International conference on: 1-6, 2017.
• [20] Ge, Z. M. ve Yang, C. H., “The generalized synchronization of a Quantum-CNN chaotic oscillator with different order system,” Chaos, Solitons and Fractals, 35: 980–990, 2008.
• [21] Chiuab, R., Gonzaleza, M. M., Mancillaa, D. L., “Implementation of a Chaotic Oscillator into a Simple Microcontroller,” IERI Procedia 4: 247–252, 2013.
• [22] Tuna, M., Fidan, C. B., Koyuncu, İ., & Pehlivan, İ., “Real time hardware implementation of the 3D chaotic oscillator which having golden-section equilibra,” 24th IEEE In Signal Processing and Communication Application Conference (SIU), pp. 1309-1312, 2016.
• [23] Koyuncu, İ. and Özcerit, A.T., “The design and realization of a new high speed FPGA-based chaotic true number generator,” Computers & Electrical Engineering, 58: 203-214, 2016.
• [24] Azzaz M.S., Taugast C., Sadoudi S., Fellah R., Dandache A., “A new auto-switched chaotic system and its FPGA implementation,” Communications in Nonlinear Science and Numerical Simulation, 18 (7), 1792-1804, 2013. [25] Lee, S. H., Kapila, V., Porfiri, M., & Panda, A. “Master–slave synchronization of continuously and intermittently coupled sampled-data chaotic oscillators,” Communications in Nonlinear Science and Numerical Simulation, 15(12), 4100-4113, 2010.
• [26] Tuna, M., & Fidan, C. B. “Electronic circuit design, implementation and FPGA-based realization of a new 3D chaotic system with single equilibrium point,” Optik-International Journal for Light and Electron Optics, 127(24), 11786-11799, 2016.
• [27] Tlelo-Cuautle, E., Rangel-Magdaleno, J. J., Pano-Azucena, A. D., Obeso-Rodelo, P. J., & Nuñez-Perez, J. C. “FPGA realization of multi-scroll chaotic oscillators,” Communications in Nonlinear Science and Numerical Simulation, 27(1-3), 66-80, 2015.
• [28] Koyuncu, İ., Şahin, İ., Gloster, C., & Sarıtekin, N. K. “A Neuron Library for Rapid Realization of Artificial Neural Networks on FPGA: A Case Study of Rössler Chaotic System,” Journal of Circuits, Systems and Computers, 26(01), 1750015. 2017.
• [29] Alçın, M., Pehlivan, İ., & Koyuncu, İ. “Hardware design and implementation of a novel ANN-based chaotic generator in FPGA,” Optik-International Journal for Light and Electron Optics, 127(13), 5500-5505, 2016.
• [30] Yuan, Z., Li, H., Miao, Y., Hu, W., & Zhu, X. “Digital-Analog Hybrid Scheme and Its Application to Chaotic Random Number Generators,” International Journal of Bifurcation and Chaos, 27(14), 1750210, 2017. [31] Jacobs, A., Cieslewski, G., George, A. D., Gordon-Ross, A., & Lam, H. “Reconfigurable fault tolerance: A comprehensive framework for reliable and adaptive FPGA-based space computing,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), 5(4), 21, 2012.
• [32] Tolba, M. F., AbdelAty, A. M., Soliman, N. S., Said, L. A., Madian, A. H., Azar, A. T., & Radwan, A. G. “FPGA implementation of two fractional order chaotic systems,” AEU-International Journal of Electronics and Communications, 78, 162-172, 2017.
• [33] Jin, C., Herder, C., Ren, L., Nguyen, P. H., Fuller, B., Devadas, S., & van Dijk, M. “Fpga implementation of a cryptographically-secure puf based on learning parity with noise,” Cryptography, 1(3), 23, 2017.
• [34] Ratnayake, K., & Amer, A. “Embedded architecture for noise-adaptive video object detection using parameter-compressed background modeling,” Journal of Real-Time Image Processing, 13(2), 397-414, 2017.
• [35] Koyuncu I, “Implementation of High Speed Tangent Sigmoid Transfer Function Approximations for Artificial Neural Network Applications on FPGA,” Advances in Electrical and Computer Engineering, 18, 79–86, 2018.
• [36] Rajagopal, K., Guessas, L., Vaidyanathan, S., Karthikeyan, A., & Srinivasan, A. “Dynamical analysis and FPGA implementation of a novel hyperchaotic system and its synchronization using adaptive sliding mode control and genetically optimized PID control,” Mathematical Problems in Engineering, 2017.
• [37] Chinna, S., Dharmar, S., & Shanmugavel, K. L. “Hardware Implementation of Road Network Extraction Using Simplified Gabor Wavelet in Field Programmable Gate Array,” International Journal of Engineering and Technology Innovation, 8(3), 200-216, 2018.