Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA

Year 2021, , 1386 - 1393, 31.12.2021

Dursun Baran

https://doi.org/10.16984/saufenbilder.877453

Abstract

Resource efficient implementation of a highly reconfigurable, parallel and pipelined FFT core that provides 1.2GS/s throughput rate with 24-bits wide input samples for the real-time spectrum analysis applications is developed and realized. Physical placement constraints are used to improve the timing performance of implemented design in FPGA. Some design techniques to reduce the memory complexities of design are also provided. Full implementation of the design is completed and implementation details are provided.

Keywords

Parallel FFT Core, Real Time Spectrum Analysis, Energy-Efficient Design, FPGA

References

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