A Survey of Hybrid Main Memory Architectures

Year 2019, Volume: 23 Issue: 1, 1 - 15, 01.02.2019

Zerrin Yıldız Çavdar , İsa Avcı Murat Koca , Ahmet Sertbaş

https://doi.org/10.16984/saufenbilder.334645

Cited By: 1

Abstract

Rapidly evolving technology, increased internet speed
and capacity, and the widespread use of mobile technologies have increased the
demands for faster applications and less power consumption of modern electronic
systems. In modern electronic systems, RAM is as effective as CPU in terms of
performance and power consumption. Though DRAM is the most commonly used type
of main memory at the present, it is being insufficient to meet the increasing
demands. In order to overcome this problem, one of the topics studied is
improving DRAM in terms of performance and power consumption. Another study to
address this increasing demand is the development of hybrid main memory
architectures. Hybrid Main Memory is one of the most recent studies on RAM.

In this research, we investigate hybrid main memory
systems for a more efficient main memory architecture.  

Keywords

Hybrid Main Memory, DRAM, Phase Change Memory/PCM, performance, energy saving

Hibrid Ana Bellek Mimarileri Hakkında Bir Araştırma

Abstract

Hızla gelişen teknoloji, artan internet hızı ve
kapasitesi, mobil teknolojilerin yaygınlaşması ile birlikte, uygulamaların
hızlı çalışması ve modern elektronik sistemlerin daha az güç tüketimi yönünde
talepler artmıştır.  Modern elektronik
sistemlerde RAM, performans ve güç tüketiminde konusunda CPU kadar etkili
olmaktadır. Günümüzde en yaygın kullanılan ana bellek türü DRAM olmakla
birlikte artan talepleri karşılaşmakta yetersiz kalmaya başlamıştır. Bu sorunun
üstesinden gelebilmek için, DRAM’in performans ve güç tüketimi açısından
geliştirilmesi üzerinde çalışılan konulardan biridir. Bu artan talebi
karşılamaya yönelik diğer bir çalışma ise hybrid ana bellek mimarilerinin
geliştirilmesi yönündedir. Hybrid Main Memory, RAM üzerine yapılan en güncel
çalışmalardandır.

Bu
araştırmada, daha verimli bir ana bellek mimarisi için hybrid ana bellek
sistemleri incelenmiştir.

Keywords

Hibrid Ana Bellek, DRAM, Faz Değişimli Bellek/PCM, performans, enerji tasarrufu

References

• L. A. Barroso ve U. Hölzle, «The Case for Energy-Proportional Computing,» IEEE Computer Society, pp. 33-37, 2007.
• C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler and T. W. Keller, "Energy Management for Commercial Servers," IEEE Computer Society, pp. 39-48, 2003.
• A. N. Udipi, N. Muralimanohar, N. Chatterjee, R. Balasubramonian, A. Davis and N. P. Jouppi, "Rethinking DRAM design and organization for energy-constrained multi-cores," in ISCA '10 Proceedings of the 37th annual international symposium on Computer architecture, Saint-Malo, 2010.
• Micron, "Micron Technology, Inc. - Hybrid Memory Cube | Memory and Storage," 16 04 2017. [Online]. Available: https://www.micron.com/products/hybrid-memory-cube.
• H. M. C. Consortium, "Hybrid Memory Cube Consortium - Home," 16 04 2017. [Online]. Available: http://hybridmemorycube.org/.
• A. Sammons and C. Sciacca, "IBM New room," 17 05 2016. [Online]. Available: https://www-03.ibm.com/press/us/en/pressrelease/49746.wss.
• S. Bagheri, A. A. Asadi, W. Kinsner and N. Sepehri, "Ferroelectric random access memory (FRAM) fatigue test with Arduino and Raspberry Pi," in 2016 IEEE International Conference on Electro Information Technology (EIT) , Grand Forks, 2016.
• Cypress, "Microcontrollers, Connectivity, Memory Solutions," 22 05 2017. [Online]. Available: http://www.cypress.com.
• T. Eshita, W. Wang, K. Nakamura, S. Mihara, H. Saito, Y. Hikosaka, K. Inoue, S. Kawashima, H. Yamaguchi and K. Nomura, "Development of ferroelectric RAM (FRAM) for mass production," in Applications of Ferroelectrics, International Workshop on Acoustic Transduction Materials and Devices & Workshop on Piezoresponse Force Microscopy (ISAF/IWATMD/PFM), 2014 Joint IEEE International Symposium on the, State College, PA, 2014.
• N. Yamada, E. Ohno, K. Nishiuchi, N. Akahira and M. Takao, "RAPID-PHASE TRANSITIONS OF GETE-SB2 TE3 PSEUDOBINARY AMORPHOUS THIN-FILMS FOR AN OPTICAL DISK MEMORY," AMER INST PHYSICS, pp. 2849-2856, 1991.
• J. Tominaga, T. Kikukawa, M. Takahashi and R. Phillips, "Structure of the optical phase change memory alloy, Ag-V-In-Sb-Te, determined by optical spectroscopy and electron diffraction," AMER INST PHYSICS, pp. 3214-3218, 1997.
• H. G. Lee, S. Baek, C. Nicopoulos and J. Kim, "An Energy- and Performance-Aware DRAM Cache Architecture for Hybrid DRAM/PCM Main Memory Systems," in 2011 IEEE 29th International Conference on Computer Design (ICCD), Amherst, MA, 2011.
• G. Wu, H. Zhang, Y. Dong and J. Hu, "CAR: Securing PCM Main Memory System with Cache Address Remapping," in 2012 IEEE 18th International Conference on Parallel and Distributed Systems, Singapore, 2012.
• L. Ramos and R. Bianchini, "Exploiting Phase-Change Memory in Cooperative Caches," in 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing, New York, NY, 2012.
• S. Kwon, D. Kim, Y. Kim, S. Yoo and S. Lee, "A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem," in 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) Design, Dresden, 2012.
• J. Meza, J. Chang, H. Yoon, O. Mutlu and P. Ranganathan, "Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management," IEEE Computer Architecture Letters, pp. 61-64, 2012.
• J. Hu, Q. Zhuge, C. J. Xue, W.-C. Tseng and E. H.-M. Sha, "Software enabled wear-leveling for hybrid PCM main memory on embedded systems," in 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Design, Grenoble, 2013.
• Z. Wang, Z. Gu and Z. Shao, "Optimizated Allocation of Data Variables to PCM/DRAM-based Hybrid Main Memory for Real-Time Embedded Systems," IEEE Embedded Systems Letters, pp. 61-64, 2014.
• L. Ramos and R. Bianchini, "Robust performance in hybrid-memory cooperative caches," Parallel Computing, p. 514–525, 2014.
• J. Hu, M. Xie, C. Pan, C. J. Xue, Q. Zhuge and E. H.-M. Sha, "Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 654-663, 2014.
• K. Kavi, S. Pianelli, G. Pisano, G. Regina and M. Ignatowski, "Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy," Journal of Systems Architecture, pp. 539-552, 2015.
• G. Wang, Y. Guan, Y. Wang and Z. Shao, "Energy-aware assignment and scheduling for hybrid main memory in embedded systems," Computing. March 2016, p. 279–301, 2016.
• Z. Zhang, Z. Jia, P. Liu and L. Ju, "Energy Efficient Real-Time Task Scheduling for Embedded Systems with Hybrid Main Memory," Journal of Signal Processing Systems, p. 69–89, 2016.
• B. Pourshirazi and Z. Zhu, "Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System," in 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), Chicago, IL, 2016.
• S. Bock, B. R. Childers, R. Melhem and D. Moss´e, "Concurrent Migration of Multiple Pages in Software-Managed Hybrid Main Memory," in 2016 IEEE 34th International Conference on Computer Design (ICCD), Scottsdale, AZ, 2016.
• J. Zhang, X. Liao, H. Jin, D. Liu, L. Lin and K. Zhao, "An Optimal Page-Level Power Management Strategy in PCM–DRAM Hybrid Memory," International Journal of Parallel Programming, pp. 4-16, 2017.
• G. Dhiman, R. Ayoub and T. Rosing, "PDRAM: A Hybrid PRAM and DRAM Main Memory System," in 2009 46th ACM/IEEE Design Automation Conference Design Automation Conference, San Francisco, CA, 2009.
• Y. Park, D.-J. Shin, S. K. Park and K. H. Park, "Power-Aware Memory Management for Hybrid Main Memory," in The 2nd International Conference on Next Generation Information Technology Next Generation Information Technology (ICNIT), Gyeongju, Korea (South), 2011.
• H. Park, S. Yoo and S. Lee, "Power Management of Hybrid DRAM/PRAM-Based Main Memory," in 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), San Diego, CA, 2011.
• J.-H. Choi, S.-M. Kim, C. Kim, K.-W. Park and K. H. Park, "OPAMP: Evaluation Framework for Optimal Page Allocation of Hybrid Main Memory Architecture," in 2012 IEEE 18th International Conference on Parallel and Distributed Systems Parallel and Distributed Systems, Singapore, 2012.
• W. Tian, Y. Zhao, L. Shi, Q. Li, J. Li, C. J. Xue, M. Li and E. Chen, "Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1271-1284, 2013.
• T. Liu, Y. Zhao, C. J. Xue and M. Li, "Power-Aware Variable Partitioning for DSPs With Hybrid PRAM and DRAM Main Memory," IEEE TRANSACTIONS ON SIGNAL PROCESSING,, pp. 3509-3520, 2013.
• M. Mao, C. Yang, Z. Xu, Y. Cao and C. Chakrabarti, "Low cost ECC schemes for improving the reliability of DRAM+ PRAM MAIN memory systems," in Signal Processing Systems (SiPS), 2014 IEEE Workshop on, Belfast, 2014.
• D. Kim, S. Yoo and S. Lee, "Hybrid Main Memory for High Bandwidth Multi-Core System," IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS, pp. 138-149, 2015.
• S.-I. Jang, S.-K. Yoon, K. Park, G.-H. Park and S.-D. Kim, "Data Classification Management with its Interfacing Structure for Hybrid SLC/MLC PRAM Main Memory," COMPUTER JOURNAL, pp. 2852-2863, 2015.
• X. Cai, L. Ju, X. Li, Z. Zhang and Z. Jia, "Energy efficient task allocation for hybrid main memory architecture," Journal of Systems Architecture, pp. 11-22, 2016.
• D. Knyaginin, G. N. Gaydadjiev and S. Per, "Crystal: A Design-Time Resource Partitioning Method for Hybrid Main Memory," in Parallel Processing (ICPP), 2014 43rd International Conference on, Minneapolis MN, 2014.
• G. Nakagawa and S. Oikawat, "Language Runtime Support for NVM/DRAM Hybrid Main Memory," in 2014 IEEE COOL Chips XVII (COOL Chips), Yokohama, 2014.
• A. Hassan, H. Vandierendonck and D. S. Nikolopoulos, "Energy-Efficient Hybrid DRAM/NVM Main Memory," in International Conference on Parallel Architecture and Compilation, San Francisco, CA, 2015.
• S. Bock, B. R. Childers, R. Melhem and D. Moss´e, "HMMSim: A Simulator for Hardware-Software Co-Design of Hybrid Main Memory," in 2015 IEEE International Conference on Grey Systems & Intelligent Services (GSIS), Leicester, United Kingdom, 2015.
• S. Bock, B. R. Childers, R. Melhem and D. Mosse, "Characterizing the Overhead of Software-Managed Hybrid Main Memory," in IEEE 23rd International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, Atlanta, GA, 2015.
• D. Ye, A. Pavuluri, C. A. Waldspurger, B. Tsang, B. Rychlik and S. Woo, "Prototyping a Hybrid Main Memory Using a Virtual Machine Monitor," in IEEE International Conference on Computer Design Computer Design, Lake Tahoe, CA, 2008.
• J. Stevens, P. Tschirhart, M.-T. Chang, I. Bhati, P. Enns, J. Greensky, Z. Chisti, S.-L. Lu and B. Jacob, "An Integrated Simulation Infrastructure For The Entire Memory Hierarchy: Cache, Dram, Nonvolatile Memory, And Disk," Intel Technology Journal, pp. 184-200, 2013.
• P. Dai, Q. Zhuge, X. Chen, W. Jiang and E. H.-M. Sha, "Effective file data-block placement for different types of page cache on hybrid main memory architectures," DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, pp. 485-506, 2013.
• Z. Chen, Y. Lu, N. Xiao and F. Liu, "A hybrid memory built by SSD and DRAM to support in-memory Big Data analytics," KNOWLEDGE AND INFORMATION SYSTEMS, pp. 335-354, 2015.
• J. B. Kwon, "Exploiting Storage Class Memory for Future Computer Systems: A Review," IETE Technical Review , pp. 218-226, 2015.
• J.-Y. Jung and R. Melhem, "Empirical, Analytical Study of Hardware-based Page Swap in Hybrid Main Memory System," in 2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Los Angeles, CA, 2016.
• W. Jing, K. Yang, Y. Lin, B. Lee, S. Yoon, Y. Ye, Y. Du and B. Chen, "Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM," IEEE Transactions on Computers, pp. 912-918, 2017.
• S.-I. Jang, C.-G. Kim and S.-D. Kim, "An Efficient DRAM Converter for Non-Volatile Based Main Memory," in IT Convergence and Security, Pyeong Chang, Korea, 2012.