Araştırma Makalesi
BibTex RIS Kaynak Göster
Yıl 2019, Cilt: 19 Sayı: 1, 12 - 21, 01.01.2019

Öz

Kaynakça

  • https://www.advantest.com/products/ic-test-systems, IC Test Systems - Advantest”, last accessed: March 2018.
  • http://www.teradyne.com/products/production-board-test "Production Board Test|Teradyne", last accessed: March 2018. http://www.teseda.com “Teseda Corporation: Silicon Failure Analysis and Yield Enhancement”, last accessed: March 2018.
  • http://www.eetimes.com/document.asp?doc_id=1175064 “Teseda breaks $200 per pin ATE barrier”, last accessed: March 2018.
  • L. Mostardini, L. Bacciarelli, L. Fanucci, L. Bertini, M. Tonarelli and M. De Marinis, ”FPGA-based low-cost automatic test equipment for digital integrated circuits,” IEEE International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, Rende, pp. 32-37, 2009.
  • J. H. M. Escobar, J. SachBe, S. Ostendorff and H. D. Wuttke, “Automatic generation of an FPGA based embedded test system for printed circuit board testing,” 13th Latin American Test Workshop (LATW), Quito, Ecuador, pp. 1-6, 2012.
  • I. Aleksejev, A. Jutman, S. Devadze, S. Odintsov and T. Wenzel, “FPGA-based synthetic instrumentation for board test,” IEEE International Test Conference, Anaheim, CA, pp. 1-10, 2012
  • A. A. Bayrakci, "ELATE: Embedded low cost automatic test equipment for FPGA based testing of digital circuits," 2017 10th International Conference on Electrical and Electronics Engineering (ELECO), Bursa, 2017, pp. 1281-1285.
  • F. S. Marques, R. P. Ribas, S. Sapatnekar, and A. I. Reis.. “A new approach to the use of satisfiability in false path detection.” Proceedings of the 15th ACM Great Lakes symposium on VLSI (GLSVLSI '05). ACM, New York, NY, USA, pp 308-311, 2005.
  • N. Eén and N. Sörensson. "An extensible SAT-solver." International conference on theory and applications of satisfiability testing. Springer, Berlin, Heidelberg, 2003.
  • L. G. e Silva, J. P. Marques Silva, L. M. Silveira and K. A. Sakallah, "Realistic delay modeling in satisfiability-based timing analysis," Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on, Monterey, CA, pp. 215-218 vol.6, 1998.
  • https://opencores.org/project/osdvu “Documented Verilog UART”, last accessed: March 2018.

FPGA Based Low Cost Automatic Test Equipment for Digital Circuits

Yıl 2019, Cilt: 19 Sayı: 1, 12 - 21, 01.01.2019

Öz

DOI: 10.26650/electrica.2018.28093


Testing of digital circuits is a crucial
problem. There are two types of Automatic Test Equipment (ATE): Very precise
but complex and expensive test equipments called high-end ATE and their
approximate but cheap alternatives called low-end ATE. In this paper we propose
a very cheap, FPGA based embedded low-cost ATE (ELATE) that is capable of
functional, speed/delay and power consumption tests. It is composed of FPGA
hardware with six FSM modules written in Verilog and a computer software (user
interface) communicating with the FPGA through UART. It can handle different
I/O combinations and can detect delay with 4ns precision. It can both visually
show the resultant voltage/current-time graphs and store them as text files.
The ATE is tested on different Design Under Test (DUT) devices like 8-bit and
12-bit adders and a square root circuit implemented on FPGA.

Cite this article as: Bayrakçi AA. FPGA
Based Low Cost Automatic Test Equipment for Digital Circuits. Electrica, 2019;
19(1): 12-21.

Kaynakça

  • https://www.advantest.com/products/ic-test-systems, IC Test Systems - Advantest”, last accessed: March 2018.
  • http://www.teradyne.com/products/production-board-test "Production Board Test|Teradyne", last accessed: March 2018. http://www.teseda.com “Teseda Corporation: Silicon Failure Analysis and Yield Enhancement”, last accessed: March 2018.
  • http://www.eetimes.com/document.asp?doc_id=1175064 “Teseda breaks $200 per pin ATE barrier”, last accessed: March 2018.
  • L. Mostardini, L. Bacciarelli, L. Fanucci, L. Bertini, M. Tonarelli and M. De Marinis, ”FPGA-based low-cost automatic test equipment for digital integrated circuits,” IEEE International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, Rende, pp. 32-37, 2009.
  • J. H. M. Escobar, J. SachBe, S. Ostendorff and H. D. Wuttke, “Automatic generation of an FPGA based embedded test system for printed circuit board testing,” 13th Latin American Test Workshop (LATW), Quito, Ecuador, pp. 1-6, 2012.
  • I. Aleksejev, A. Jutman, S. Devadze, S. Odintsov and T. Wenzel, “FPGA-based synthetic instrumentation for board test,” IEEE International Test Conference, Anaheim, CA, pp. 1-10, 2012
  • A. A. Bayrakci, "ELATE: Embedded low cost automatic test equipment for FPGA based testing of digital circuits," 2017 10th International Conference on Electrical and Electronics Engineering (ELECO), Bursa, 2017, pp. 1281-1285.
  • F. S. Marques, R. P. Ribas, S. Sapatnekar, and A. I. Reis.. “A new approach to the use of satisfiability in false path detection.” Proceedings of the 15th ACM Great Lakes symposium on VLSI (GLSVLSI '05). ACM, New York, NY, USA, pp 308-311, 2005.
  • N. Eén and N. Sörensson. "An extensible SAT-solver." International conference on theory and applications of satisfiability testing. Springer, Berlin, Heidelberg, 2003.
  • L. G. e Silva, J. P. Marques Silva, L. M. Silveira and K. A. Sakallah, "Realistic delay modeling in satisfiability-based timing analysis," Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on, Monterey, CA, pp. 215-218 vol.6, 1998.
  • https://opencores.org/project/osdvu “Documented Verilog UART”, last accessed: March 2018.
Toplam 11 adet kaynakça vardır.

Ayrıntılar

Birincil Dil İngilizce
Konular Mühendislik
Bölüm Makaleler
Yazarlar

Alp Arslan Bayrakci

Yayımlanma Tarihi 1 Ocak 2019
Yayımlandığı Sayı Yıl 2019 Cilt: 19 Sayı: 1

Kaynak Göster

APA Bayrakci, A. A. (2019). FPGA Based Low Cost Automatic Test Equipment for Digital Circuits. Electrica, 19(1), 12-21.
AMA Bayrakci AA. FPGA Based Low Cost Automatic Test Equipment for Digital Circuits. Electrica. Ocak 2019;19(1):12-21.
Chicago Bayrakci, Alp Arslan. “FPGA Based Low Cost Automatic Test Equipment for Digital Circuits”. Electrica 19, sy. 1 (Ocak 2019): 12-21.
EndNote Bayrakci AA (01 Ocak 2019) FPGA Based Low Cost Automatic Test Equipment for Digital Circuits. Electrica 19 1 12–21.
IEEE A. A. Bayrakci, “FPGA Based Low Cost Automatic Test Equipment for Digital Circuits”, Electrica, c. 19, sy. 1, ss. 12–21, 2019.
ISNAD Bayrakci, Alp Arslan. “FPGA Based Low Cost Automatic Test Equipment for Digital Circuits”. Electrica 19/1 (Ocak 2019), 12-21.
JAMA Bayrakci AA. FPGA Based Low Cost Automatic Test Equipment for Digital Circuits. Electrica. 2019;19:12–21.
MLA Bayrakci, Alp Arslan. “FPGA Based Low Cost Automatic Test Equipment for Digital Circuits”. Electrica, c. 19, sy. 1, 2019, ss. 12-21.
Vancouver Bayrakci AA. FPGA Based Low Cost Automatic Test Equipment for Digital Circuits. Electrica. 2019;19(1):12-21.