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SINGLE BANK DUAL-PORT MEMORY-BASED FFT FOR FIELD PROGRAMMABLE GATE ARRAYS

Yıl 2018, Cilt: 19 Sayı: 4, 796 - 804, 31.12.2018
https://doi.org/10.18038/aubtda.423280

Öz

A new efficient memory-based FFT calculation method is presented using dual-port memories. Algorithm mainly targets Field Programmable Gate Arrays (FPGA). A semi-in-place calculation of FFT stages is presented to have both reads and writes in a single clock while keeping the memory size equal to the FFT size. The "semi-" word implies that the writes are not to the original/expected position. At each intermediate calculation, the outputs are written to the position where the reads are done so that the unused data is not overwritten. Compared to multi-bank memory FFT approaches, proposed memory addressing schema is both simpler to logically establish and requires lower count of logical elements. It is shown that the proposed approach accomplishes FFT task in lowest count of clock cycles among the single bank memory-based FFT algorithms.

Kaynakça

  • Cooley JW, Tukey JW. An algorithm for the machine calculation of complex Fourier series. Math Comput 1965; 19: 297-301.
  • Johnson LG. Conflict free memory addressing for dedicated FFT hardware. IEEE Trans Circuits Syst II, Analog Digit Signal Process 1992; 39, 5: 312–316.
  • Hidalgo JA, Lopez J, Arguello F, Zapata EL. Area-efficient architecture for fast Fourier transform. IEEE Trans Circuits Syst II, Analog Digit. Signal Process 1999; 46, 2: 187–193.
  • Chen J, Hu J, Lee S, Sobelman GE. Hardware efficient mixed radix-25/16/9 FFT for LTE systems. IEEE Trans Very Large Scale Integr (VLSI) Syst 2015; 23, 2: 221–229.
  • Xia K, Wu B, Xiong T, Ye T. A memory-based FFT processor design with generalized efficient conflict-free address schemes. IEEE Trans Very Large Scale Integr (VLSI) Syst 2017; 25, 6: 1919-1929.
  • Hsiao CF, Chen Y, Lee CY. A generalized mixed-radix algorithm for memory-based FFT processors. IEEE Trans Circuits Syst II, Express Briefs 2010; 57, 1: 26–30.
  • Jo BG, Sunwoo MH. New continuous-flow mixed-radix (CFMR) FFT processor using novel in-place strategy. IEEE Trans Circuits Syst I, Reg Papers 2005; 52, 5: 911–919.
  • Baek J, Choi K. New address generation scheme for memory based FFT processor using multiple radix-2 butterflies. In: Proc. Int. SoC Design Conf; Nov 2008; 1:I-273–I-276.
  • Altera. DFT/IDFT Reference Design 2007; [Online]. Available 2018: http://www.altera.com.
  • Xilinx. LogiCORE IP Discrete Fourier Transform V9.0 2017; [Online]. Available 2018: http://www.xilinx.com.
  • Sansaloni T, Pérez-Pascual A, Torres V, Valls J. Scheme for reducing the storage requirements of FFT twiddle factors on FPGAs. J VLSI Signal Proc 2007; 47: 183-187.
  • De Caro D, Strollo AGM. High-Performance Direct Digital Frequency Synthesizers Using Piecewise-Polynomial Approximation. IEEE Trans Circuits Syst I:Regular Papers 2005; 52, 2: 324-337.
Yıl 2018, Cilt: 19 Sayı: 4, 796 - 804, 31.12.2018
https://doi.org/10.18038/aubtda.423280

Öz

Kaynakça

  • Cooley JW, Tukey JW. An algorithm for the machine calculation of complex Fourier series. Math Comput 1965; 19: 297-301.
  • Johnson LG. Conflict free memory addressing for dedicated FFT hardware. IEEE Trans Circuits Syst II, Analog Digit Signal Process 1992; 39, 5: 312–316.
  • Hidalgo JA, Lopez J, Arguello F, Zapata EL. Area-efficient architecture for fast Fourier transform. IEEE Trans Circuits Syst II, Analog Digit. Signal Process 1999; 46, 2: 187–193.
  • Chen J, Hu J, Lee S, Sobelman GE. Hardware efficient mixed radix-25/16/9 FFT for LTE systems. IEEE Trans Very Large Scale Integr (VLSI) Syst 2015; 23, 2: 221–229.
  • Xia K, Wu B, Xiong T, Ye T. A memory-based FFT processor design with generalized efficient conflict-free address schemes. IEEE Trans Very Large Scale Integr (VLSI) Syst 2017; 25, 6: 1919-1929.
  • Hsiao CF, Chen Y, Lee CY. A generalized mixed-radix algorithm for memory-based FFT processors. IEEE Trans Circuits Syst II, Express Briefs 2010; 57, 1: 26–30.
  • Jo BG, Sunwoo MH. New continuous-flow mixed-radix (CFMR) FFT processor using novel in-place strategy. IEEE Trans Circuits Syst I, Reg Papers 2005; 52, 5: 911–919.
  • Baek J, Choi K. New address generation scheme for memory based FFT processor using multiple radix-2 butterflies. In: Proc. Int. SoC Design Conf; Nov 2008; 1:I-273–I-276.
  • Altera. DFT/IDFT Reference Design 2007; [Online]. Available 2018: http://www.altera.com.
  • Xilinx. LogiCORE IP Discrete Fourier Transform V9.0 2017; [Online]. Available 2018: http://www.xilinx.com.
  • Sansaloni T, Pérez-Pascual A, Torres V, Valls J. Scheme for reducing the storage requirements of FFT twiddle factors on FPGAs. J VLSI Signal Proc 2007; 47: 183-187.
  • De Caro D, Strollo AGM. High-Performance Direct Digital Frequency Synthesizers Using Piecewise-Polynomial Approximation. IEEE Trans Circuits Syst I:Regular Papers 2005; 52, 2: 324-337.
Toplam 12 adet kaynakça vardır.

Ayrıntılar

Birincil Dil İngilizce
Konular Mühendislik
Bölüm Makaleler
Yazarlar

Erol Seke Bu kişi benim

Zeynep Kaya Bu kişi benim

Yayımlanma Tarihi 31 Aralık 2018
Yayımlandığı Sayı Yıl 2018 Cilt: 19 Sayı: 4

Kaynak Göster

AMA Seke E, Kaya Z. SINGLE BANK DUAL-PORT MEMORY-BASED FFT FOR FIELD PROGRAMMABLE GATE ARRAYS. Eskişehir Technical University Journal of Science and Technology A - Applied Sciences and Engineering. Aralık 2018;19(4):796-804. doi:10.18038/aubtda.423280