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Two Novel Subthreshold Logic Families for Area and Ultra low-Energy Efficient Applications: DTGDI & SBBGDI

Yıl 2017, Cilt: 30 Sayı: 4, 283 - 294, 11.12.2017

Öz

Two novel area and ultra
low-energy efficient subthreshold logic families: Dynamic Threshold Gate
Diffusion Input (DTGDI) and Swapped Body Bias Gate Diffusion Input (SBBGDI)
are
introduced. These logic families examine the effectiveness of GDI based
circuits over the Conventional CMOS (C-CMOS) logic circuits using subthreshold
optimal area overhead free body biasing schemes. The basic logic gates OR, AND
and XOR are designed using the proposed DTGDI and SBBGDI logic. To analyze the
performance, a full adder cell is implemented. The simulations are performed in
Cadence 45nm technology with 0.2V supply voltage. The simulation results show
that the proposed DTGDI full adder circuit with layout area of only 6.891µm2 offers more than 41% savings in energy ,78%
savings in EDP than the Conventional CMOS (C-CMOS) and more than 12% energy savings, 27%
savings in EDP than the GDI. Whereas, the SBBGDI full adder circuit with layout
area of only 5.654 µm2 offers more
than 47% savings in energy ,90% savings in EDP than the C-CMOS and more than 24% energy savings, 67%
savings in EDP than the GDI.

Kaynakça

  • [1] Alice Wang B, Chandrakasan A "Sub-threshold Design for Ultra Low-Power Systems". Springer, New York, NY, (2006) [2] Assaderaghi F, Sinitsky D, Parke S, Bokor J, Ko PK, Hu C, “A dynamic threshold voltage mosfet (DTMOS) for ultra-low voltage operation” Proceedings of 1994 IEEE International Electron Devices Meeting, pp: 809-812, (1994) [3] Huang SF, Wann C, Huang YS, Lin CY, Schafbauer T, Cheng SM, Cheng YC, Vietzke D, Eller M, Lin C, Ye Q, Rovedo N, Biesemans S, Nguyen P, Dennard R, Chen B, “Scalability and biasing strategy for cmos with active well bias” Symposium on VLSI Technology, pp 107-108, (2001) [4] Kao JT, Miyazaki M, Chandrakasan A, “A 175-mv multiply- accumulate unit using an adaptive supply voltage and body bias architecture”, IEEE Journal of Solid-State Circuits 37(11), pp:1545-1554, (2002) [5] Kuroda T, Fujita T, Mita S, Nagamatsu T, Yoshioka S, Suzuki K, Sano F, Norishima M, Murota M, Kako M, Kinugawa M, Kakumu M, Sakurai T, “A 0.9-v, 150-mhz, 10-mw, 4 mm2, 2-d discrete cosine transform core processor with variable threshold-voltage (vt) scheme”, IEEE Journal of Solid-State Circuits 31(11), pp:1770-1779, (1996) [6] Lindert N, Sugii T, Tang S, Hu C, “Dynamic threshold pass- transistor logic for improved delay at lower power supply voltages”. IEEE Journal of Solid-State Circuits 34(1), pp:85-89, (1999) [7] Narendra S, Tschanz J, Hofsheier J, Bloechel B, Vangal S, Hoskote Y, Tang S, Somasekhar D, Keshavarzi A, Erraguntla V, Dermer G, Borkar N, Borkar S, De V, “Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique”, IEEE International Solid-State Circuits Conference, pp:156-518, (2004) [8] Morgenshtein A, Fish A, Wagner IA, “Gate-di_usion input (GDI): A power efficient method for digital combinatorial circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10(5), pp:566-581, (2002) [9] Sakthivel R, Kittur H, “Energy efficient low area error tolerant adder with higher accuracy”, Circuits, Systems, and Signal Processing, 33(8), pp: 2625-2641, (2014) [10] Navi K, Moaiyeri MH, Mirzaee RF, Hashemipour O, Nezhad BM, “Two new low-power full adders based on majority-not gates”, Microelectronics Journal, 40(1), pp:126-130, (2009) [11] Rabaey JM, chandrakasan A, Nikolic B, “Digital Integrated Circuits: A Design Perspective”, Prentice-Hall, Inc., Upper Saddle River, NJ, USA, (1996) [12] Zimmermann R, Fichtner W, “Low-power logic styles: CMOS versus pass-transistor logic”, IEEE Journal of Solid-State Circuits, 32(7), PP:1079-1090, (1997) [13] Morgenshtein A, Shwartz I, Fish A, “Gate di_usion input (gdi) logic in standard cmos nanoscale process”, IEEE 26th Convention Electrical and Electronics Engineers, pp:776-780, (2010) [14] Lee PM, Hsu CH, Hung YH, “Novel 10-T full adders realized by GDI structure”, International Symposium on Integrated Circuits, ISIC '07., pp: 115-118, (2007)
Yıl 2017, Cilt: 30 Sayı: 4, 283 - 294, 11.12.2017

Öz

Kaynakça

  • [1] Alice Wang B, Chandrakasan A "Sub-threshold Design for Ultra Low-Power Systems". Springer, New York, NY, (2006) [2] Assaderaghi F, Sinitsky D, Parke S, Bokor J, Ko PK, Hu C, “A dynamic threshold voltage mosfet (DTMOS) for ultra-low voltage operation” Proceedings of 1994 IEEE International Electron Devices Meeting, pp: 809-812, (1994) [3] Huang SF, Wann C, Huang YS, Lin CY, Schafbauer T, Cheng SM, Cheng YC, Vietzke D, Eller M, Lin C, Ye Q, Rovedo N, Biesemans S, Nguyen P, Dennard R, Chen B, “Scalability and biasing strategy for cmos with active well bias” Symposium on VLSI Technology, pp 107-108, (2001) [4] Kao JT, Miyazaki M, Chandrakasan A, “A 175-mv multiply- accumulate unit using an adaptive supply voltage and body bias architecture”, IEEE Journal of Solid-State Circuits 37(11), pp:1545-1554, (2002) [5] Kuroda T, Fujita T, Mita S, Nagamatsu T, Yoshioka S, Suzuki K, Sano F, Norishima M, Murota M, Kako M, Kinugawa M, Kakumu M, Sakurai T, “A 0.9-v, 150-mhz, 10-mw, 4 mm2, 2-d discrete cosine transform core processor with variable threshold-voltage (vt) scheme”, IEEE Journal of Solid-State Circuits 31(11), pp:1770-1779, (1996) [6] Lindert N, Sugii T, Tang S, Hu C, “Dynamic threshold pass- transistor logic for improved delay at lower power supply voltages”. IEEE Journal of Solid-State Circuits 34(1), pp:85-89, (1999) [7] Narendra S, Tschanz J, Hofsheier J, Bloechel B, Vangal S, Hoskote Y, Tang S, Somasekhar D, Keshavarzi A, Erraguntla V, Dermer G, Borkar N, Borkar S, De V, “Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique”, IEEE International Solid-State Circuits Conference, pp:156-518, (2004) [8] Morgenshtein A, Fish A, Wagner IA, “Gate-di_usion input (GDI): A power efficient method for digital combinatorial circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10(5), pp:566-581, (2002) [9] Sakthivel R, Kittur H, “Energy efficient low area error tolerant adder with higher accuracy”, Circuits, Systems, and Signal Processing, 33(8), pp: 2625-2641, (2014) [10] Navi K, Moaiyeri MH, Mirzaee RF, Hashemipour O, Nezhad BM, “Two new low-power full adders based on majority-not gates”, Microelectronics Journal, 40(1), pp:126-130, (2009) [11] Rabaey JM, chandrakasan A, Nikolic B, “Digital Integrated Circuits: A Design Perspective”, Prentice-Hall, Inc., Upper Saddle River, NJ, USA, (1996) [12] Zimmermann R, Fichtner W, “Low-power logic styles: CMOS versus pass-transistor logic”, IEEE Journal of Solid-State Circuits, 32(7), PP:1079-1090, (1997) [13] Morgenshtein A, Shwartz I, Fish A, “Gate di_usion input (gdi) logic in standard cmos nanoscale process”, IEEE 26th Convention Electrical and Electronics Engineers, pp:776-780, (2010) [14] Lee PM, Hsu CH, Hung YH, “Novel 10-T full adders realized by GDI structure”, International Symposium on Integrated Circuits, ISIC '07., pp: 115-118, (2007)
Toplam 1 adet kaynakça vardır.

Ayrıntılar

Bölüm Electrical & Electronics Engineering
Yazarlar

Kishore Sanapala 0000-0002-9450-9574

Yayımlanma Tarihi 11 Aralık 2017
Yayımlandığı Sayı Yıl 2017 Cilt: 30 Sayı: 4

Kaynak Göster

APA Sanapala, K. (2017). Two Novel Subthreshold Logic Families for Area and Ultra low-Energy Efficient Applications: DTGDI & SBBGDI. Gazi University Journal of Science, 30(4), 283-294.
AMA Sanapala K. Two Novel Subthreshold Logic Families for Area and Ultra low-Energy Efficient Applications: DTGDI & SBBGDI. Gazi University Journal of Science. Aralık 2017;30(4):283-294.
Chicago Sanapala, Kishore. “Two Novel Subthreshold Logic Families for Area and Ultra Low-Energy Efficient Applications: DTGDI & SBBGDI”. Gazi University Journal of Science 30, sy. 4 (Aralık 2017): 283-94.
EndNote Sanapala K (01 Aralık 2017) Two Novel Subthreshold Logic Families for Area and Ultra low-Energy Efficient Applications: DTGDI & SBBGDI. Gazi University Journal of Science 30 4 283–294.
IEEE K. Sanapala, “Two Novel Subthreshold Logic Families for Area and Ultra low-Energy Efficient Applications: DTGDI & SBBGDI”, Gazi University Journal of Science, c. 30, sy. 4, ss. 283–294, 2017.
ISNAD Sanapala, Kishore. “Two Novel Subthreshold Logic Families for Area and Ultra Low-Energy Efficient Applications: DTGDI & SBBGDI”. Gazi University Journal of Science 30/4 (Aralık 2017), 283-294.
JAMA Sanapala K. Two Novel Subthreshold Logic Families for Area and Ultra low-Energy Efficient Applications: DTGDI & SBBGDI. Gazi University Journal of Science. 2017;30:283–294.
MLA Sanapala, Kishore. “Two Novel Subthreshold Logic Families for Area and Ultra Low-Energy Efficient Applications: DTGDI & SBBGDI”. Gazi University Journal of Science, c. 30, sy. 4, 2017, ss. 283-94.
Vancouver Sanapala K. Two Novel Subthreshold Logic Families for Area and Ultra low-Energy Efficient Applications: DTGDI & SBBGDI. Gazi University Journal of Science. 2017;30(4):283-94.