The impact transconductance parameter and threshold voltage of MOSFET’s in static characteristics of CMOS inverter

Yıl 2017, Cilt: 2 Sayı: 3, 135 - 148, 14.11.2017

Milaim Zabeli Nebi Caka Myzafere Limani Qamil Kabashi

https://doi.org/10.28978/nesciences.358859

Öz

The objective of this paper is to research the impact of electrical and physical parameters that
characterize the complementary MOSFET transistors (NMOS and PMOS transistors) in the CMOS
inverter for static mode of operation. In addition to this, the paper also aims at exploring the
directives that are to be followed during the design phase of the CMOS inverters that enable
designers to design the CMOS inverters with the best possible performance, depending on
operation conditions. The CMOS inverter designed with the best possible features also enables the
designing of the CMOS logic circuits with the best possible performance, according to the
operation conditions and designers’ requirements.

Anahtar Kelimeler

CMOS inverter, threshold voltage, voltage critical value, noise margins, transconductance parameter

Kaynakça

• Baker, R. J. (2010). CMOS Circuit Design, Layout and Simulation (3rd ed.). New Jersey, USA: John Wiley & Songs. Caka, N., Zabeli, M., Limani, M., & Kabashi, Q. (2010). Role of driver and load transistor (MOSFET) parameters on pseudo-NMOS logic design. WSEAS Transactions on Circuits and Systems, 8, 557-566.
• Chang, C. H., Liu, C. O., Zhang, L., & Kong, Z. H. (2016). Sizing of SRAM cell with voltage biasing techniques for reliability enhancement of memory and PUF functions. Journal of Low Power Electronics and Applications, 6, 1-16. Kang, S., & Leblebici, Y. (2016). CMOS Digital Integrated Circuits (4th ed.). New York, USA: McGraw-Hill.
• Karl, E., Wang, Y., Ng, Y. G., Guo, Z., Hamzaogly, F., Meterelliyoz, M., . . . Bohr, M. (2013). A 4.6 GHZ 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated, read and write assist circuitry. IEEE Journal of Solid-State Circuits, 48, 150-158.
• Lundager, K., Zeinali, B., Tohidi, M., Madsen, J. K., & Moradi, F. (2016). Low power design for future wearable and implantable devices. Journal of Low Power Elektronics and Applications, 6(4), 1-20.
• Pal, A. (2015). Low-Power VLSI Circuits and Systems (NA ed.). New Delhi, India: Springer.
• Plummer, J. D., Deal, M. D., & Griffin, P. B. (2009). Silicon VLSI Technology: Fundamentals, Practise and Modeling (NA ed.). New Delhi, India: Pearson Education.
• Rani, L. V., & Latha, M. M. (2016). Pass transistor-based pull-up/pull-down insertion technique for leakage power optimization in CMOS VLSI circuits. Circuts, System, Signal Processing, 35(11), 4139-4152.
• Salman, E., & Friedman, E. G. (2012). High Performance Integrated Circuits Design (1st ed.). New York, USA: McGraw-Hill.
• Sedra, A., & Smith, K. C. (2015). Microelectronic Circuits (8th ed.). New York, USA: Oxford University Press. Taur, Y., & Ning, T. H. (2013). Fundamentals of Modern VLSI Devices (2nd ed.). Cambridge, UK: Cambridge University Press.
• Uddin, M. J., Nordin, A. N., Reaz, M. B., & Bhuiyan, M. A. (2013). A CMOS power splitter for 2.45 GHz ISM band RFID rider in 0.18 um CMOS technology. Tehnicki Vjesnik, 20(1), 125-129.
• Weste, N. H., & Harris, D. M. (2011). CMOS VLSI Design: A Circuits and System Perspective (4th ed.). Boston, USA: Pearson Education.
• Zant, P. V. (2014). Microchip Fabrication: A Practical Guide to Semiconductor Processing (6th ed.). New York, USA: McGraw-Hill.
• Zeinali, B., Madsen, J. K., Raghavan, P., & Moradi, F. (2015). Sub-threshold SRAM design in 14 nm FinFET technology with impoved access time and leakage power. Proceedings of the IEEE Computer Society Annual Symposium on VLSI, (pp. 74-79). Montpellier.
• Zhang, H., Huang, M., Zhang, Y., Li, X., & Yoshihara, T. (2013). A nano-power switched-capacitor voltage reference using body effect in MOSFETs for application in subthreshold LSI. Proceedings of the IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), (pp. 101-125). Hong Kong.