Araştırma Makalesi
BibTex RIS Kaynak Göster
Yıl 2021, , 1386 - 1393, 31.12.2021
https://doi.org/10.16984/saufenbilder.877453

Öz

Destekleyen Kurum

BİLİŞİM ve BİLGİ GÜVENLİĞİ İLERİ TEKNOLOJİLER ARAŞTIRMA MERKEZİ (BILGEM) - TÜBİTAK

Kaynakça

  • [1] C. Fager, T. Eriksson, F. Barradas, K. Hausmair, T. Cunha and J. C. Pedro, "Linearity and Efficiency in 5G Transmitters: New Techniques for Analyzing Efficiency, Linearity, and Linearization in a 5G Active Antenna Transmitter Context," in IEEE Microwave Magazine, vol. 20, no. 5, pp. 35-49, May 2019.
  • [2] C. Eddington, B. Ray, “Using parallel FFT for multi-gigahertz FPGA signal processing”, EE Times Magazine, https://www.eetimes.com/using-parallel-fft-for-multi-gigahertz-fpga-signal-processing/
  • [3] X. Zou, Y. Liu, Y. Zhang, P. Liu, F. Li and Y. Wu, "FPGA Implementation of Full Parallel and Pipelined FFT," 2012 8th International Conference on Wireless Communications, Networking and Mobile Computing, Shanghai, 2012, pp. 1-4.
  • [4] H. Kanders, T. Mellqvist, M. Garrido, K. Palmkvist and O. Gustafsson, "A 1 Million-Point FFT on a Single FPGA," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 10, pp. 3863-3873, Oct. 2019
  • [5] M. Dreschmann et al., "Implementation of an ultra-high speed 256-point FFT for Xilinx Virtex-6 devices," 2011 9th IEEE International Conference on Industrial Informatics, Caparica, Lisbon, 2011, pp. 829-834.
  • [6] Shousheng He; Torkelson, M.; “ A new approach to pipeline FFT processor ,” Parallel Processing Symposium, 1996, Proceedings of IPPS ’96, The 10th International, April 1996.
  • [7] V. Iglesias, J. Grajal, M. A. Sánchez and M. López-Vallejo, "Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms," in IEEE Transactions on Instrumentation and Measurement, vol. 64, no. 2, pp. 338-355, Feb. 2015.
  • [8] https://www.xilinx.com/products/silicon-devices/fpga.html
  • [9] https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf
  • [10] S. Rapuano and F. J. Harris, "An introduction to FFT and time domain windows," in IEEE Instrumentation & Measurement Magazine, vol. 10, no. 6, pp. 32-44, December 2007.
  • [11] https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_1/pg109-xfft.pdf
  • [12] B. R. Zeydel, D. Baran and V. G. Oklobdzija, "Energy-Efficient Design Methodologies: High-Performance VLSI Adders," in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1220-1233, June 2010.
  • [13] https://www.pentek.com/products/detail.cfm?model=78741
  • [14] https://www.xilinx.com/products/design-tools/planahead.html
  • [15] Palmer J., Nelson B. (2004) A Parallel FFT Architecture for FPGAs. In: Becker J., Platzner M., Vernalde S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin,
  • [16] K. Nguyen, J. Zheng, Y. He and B. Shah, "A high-throughput, adaptive FFT architecture for FPGA-based space-borne data processors," 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010, pp. 121-126

Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA

Yıl 2021, , 1386 - 1393, 31.12.2021
https://doi.org/10.16984/saufenbilder.877453

Öz

Resource efficient implementation of a highly reconfigurable, parallel and pipelined FFT core that provides 1.2GS/s throughput rate with 24-bits wide input samples for the real-time spectrum analysis applications is developed and realized. Physical placement constraints are used to improve the timing performance of implemented design in FPGA. Some design techniques to reduce the memory complexities of design are also provided. Full implementation of the design is completed and implementation details are provided.

Kaynakça

  • [1] C. Fager, T. Eriksson, F. Barradas, K. Hausmair, T. Cunha and J. C. Pedro, "Linearity and Efficiency in 5G Transmitters: New Techniques for Analyzing Efficiency, Linearity, and Linearization in a 5G Active Antenna Transmitter Context," in IEEE Microwave Magazine, vol. 20, no. 5, pp. 35-49, May 2019.
  • [2] C. Eddington, B. Ray, “Using parallel FFT for multi-gigahertz FPGA signal processing”, EE Times Magazine, https://www.eetimes.com/using-parallel-fft-for-multi-gigahertz-fpga-signal-processing/
  • [3] X. Zou, Y. Liu, Y. Zhang, P. Liu, F. Li and Y. Wu, "FPGA Implementation of Full Parallel and Pipelined FFT," 2012 8th International Conference on Wireless Communications, Networking and Mobile Computing, Shanghai, 2012, pp. 1-4.
  • [4] H. Kanders, T. Mellqvist, M. Garrido, K. Palmkvist and O. Gustafsson, "A 1 Million-Point FFT on a Single FPGA," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 10, pp. 3863-3873, Oct. 2019
  • [5] M. Dreschmann et al., "Implementation of an ultra-high speed 256-point FFT for Xilinx Virtex-6 devices," 2011 9th IEEE International Conference on Industrial Informatics, Caparica, Lisbon, 2011, pp. 829-834.
  • [6] Shousheng He; Torkelson, M.; “ A new approach to pipeline FFT processor ,” Parallel Processing Symposium, 1996, Proceedings of IPPS ’96, The 10th International, April 1996.
  • [7] V. Iglesias, J. Grajal, M. A. Sánchez and M. López-Vallejo, "Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms," in IEEE Transactions on Instrumentation and Measurement, vol. 64, no. 2, pp. 338-355, Feb. 2015.
  • [8] https://www.xilinx.com/products/silicon-devices/fpga.html
  • [9] https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf
  • [10] S. Rapuano and F. J. Harris, "An introduction to FFT and time domain windows," in IEEE Instrumentation & Measurement Magazine, vol. 10, no. 6, pp. 32-44, December 2007.
  • [11] https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_1/pg109-xfft.pdf
  • [12] B. R. Zeydel, D. Baran and V. G. Oklobdzija, "Energy-Efficient Design Methodologies: High-Performance VLSI Adders," in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1220-1233, June 2010.
  • [13] https://www.pentek.com/products/detail.cfm?model=78741
  • [14] https://www.xilinx.com/products/design-tools/planahead.html
  • [15] Palmer J., Nelson B. (2004) A Parallel FFT Architecture for FPGAs. In: Becker J., Platzner M., Vernalde S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin,
  • [16] K. Nguyen, J. Zheng, Y. He and B. Shah, "A high-throughput, adaptive FFT architecture for FPGA-based space-borne data processors," 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010, pp. 121-126
Toplam 16 adet kaynakça vardır.

Ayrıntılar

Birincil Dil İngilizce
Konular Elektrik Mühendisliği
Bölüm Araştırma Makalesi
Yazarlar

Dursun Baran 0000-0001-9277-3796

Yayımlanma Tarihi 31 Aralık 2021
Gönderilme Tarihi 9 Şubat 2021
Kabul Tarihi 2 Kasım 2021
Yayımlandığı Sayı Yıl 2021

Kaynak Göster

APA Baran, D. (2021). Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA. Sakarya University Journal of Science, 25(6), 1386-1393. https://doi.org/10.16984/saufenbilder.877453
AMA Baran D. Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA. SAUJS. Aralık 2021;25(6):1386-1393. doi:10.16984/saufenbilder.877453
Chicago Baran, Dursun. “Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA”. Sakarya University Journal of Science 25, sy. 6 (Aralık 2021): 1386-93. https://doi.org/10.16984/saufenbilder.877453.
EndNote Baran D (01 Aralık 2021) Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA. Sakarya University Journal of Science 25 6 1386–1393.
IEEE D. Baran, “Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA”, SAUJS, c. 25, sy. 6, ss. 1386–1393, 2021, doi: 10.16984/saufenbilder.877453.
ISNAD Baran, Dursun. “Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA”. Sakarya University Journal of Science 25/6 (Aralık 2021), 1386-1393. https://doi.org/10.16984/saufenbilder.877453.
JAMA Baran D. Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA. SAUJS. 2021;25:1386–1393.
MLA Baran, Dursun. “Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA”. Sakarya University Journal of Science, c. 25, sy. 6, 2021, ss. 1386-93, doi:10.16984/saufenbilder.877453.
Vancouver Baran D. Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA. SAUJS. 2021;25(6):1386-93.

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