An Error Correction Structure for DH-PIM Transmission Method

Abstract

In the study, the performance analysis of error correction structures has been investigated for the DH-PIM method which is proposed for optical communication systems. A suitable system model for erasure and false alarm errors are obtained to join the Visible Light Communication (VLC) Systems. A theoretical framework is given for the model in this paper. New digital circuit based architecture is improved for erasure error structure in a FPGA (Field Programmable Gate Arrays) complier Quartus. The results are investigated in the Modelsim-Altera simulator in terms of the time chart. According to obtained results, it is shown that proposed digital circuit based architecture can successfully correct the error slots. Additionally, the performance of slot error rate has been analyzed for both erasure and false alarm errors of which the theoretical frameworks are obtained. It is shown from results that erasure error correction system (S-DHPIM) has better slot error rate performance than that of traditional DH-PIM (G-DHPIM). Addition to this, it is indicated that DH-PIM with erasure and false alarm correction structure (SY-DHPIM) gives better slot error performance compared with the S-DHPIM.

Keywords

• DH-PIM
• FPGA
• Error Correction
• VLC

DH-PIM İletim Yöntemi için Bir Hata Düzeltme Yapısı

Abstract

Yapılan çalışmada optik haberleşme sistemleri için önerilen DH-PIM yöntemi için hata düzeltme yapılarının performans analizi incelenmiştir. Silme ve Yanlış Alarm hataları için uygulanabilir bir sistem modeli Görünür Işık Haberleşme (Visible Light Communication: VLC) sistemlerine entegre edebilmek için elde edilmiştir. Yapılan çalışmada model için terorik bir analiz verilmiştir. Silme hatası yapısı için bir FPGA (Field Programmable Gate Arrays: Alanda Programlanabilir Kapı Dizileri) derleyicisi Quartus programında yeni bir sayısal devre tabanlı mimari geliştirilmiştir. Sonuçlar Modelsim-Altera Programında zamana göre incelenmiştir. Alınan sonuçlara göre, önerilen sayısal devre tabanlı hata düzeltme yapısının başarılı bir şekilde hatalı slotları düzeltebildiği görülmüştür. Ayrıca teorik ifadesi elde edilen hem silme hatası hem de yanlış alarm hatası için slot hata oranı performansları incelenmiştir. Elde edilen sonuçlara göre geleneksel DH-PIM (G-DHPIM) sistemine göre sadece silme hatası uygulanan sistem (S-DHPIM) daha iyi bir slot hata performansı vermiştir. Ayrıca, hem silme hatası hem de yanlış alarm hatası uygulanan DH-PIM sisteminin (SY-DHPIM) de S-DHPIM göre daha iyi bir slot hata performansı verdiği izlenmiştir.

Keywords

• DH-PIM
• FPGA
• Hata Düzeltme
• VLC

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