Plaka Bölgesi Tespiti Problemi için Yapay Arı Koloni Algoritması ile YSA Eğitiminin APKD’de Gerçeklenmesi

Year 2021, , 446 - 457, 30.06.2021

Mehmet Ali Çavuşlu

https://doi.org/10.35193/bseufbd.884109

Cited By: 1

Abstract

Son zamanlarda Yapay Sinir Ağı (YSA) eğitimlerinde türev bilgisi gerektiren algoritmalara alternatif olarak küresel arama özelliğine sahip evrimsel algoritmalar sıklıkla kullanılmaktadır. Bu çalışmada YSA eğitimi, evrimsel algoritmalardan Yapay Arı Koloni (YAK) algoritması ile Alan Programlanabilir Kapı Dizileri (APKD) üzerinde donanımsal gerçekleştirilmiştir. APKD tabanlı gerçeklemede sayı formatı ve aktivasyon fonksiyonu yaklaşımı maliyet, hız ve hata duyarlılığı açısından önem arz etmektedir. Çalışmada yüksek hassasiyet ve dinamiklik özelliklerine sahip IEEE 754 kayan noktalı sayı formatı seçilmiştir. Üssel fonksiyonun donanımsal gerçeklenmesinin zor olması nedeni ile aktivasyon fonksiyonunun donanımsal gerçeklenmesinde matematiksel yaklaşım kullanılmıştır. Çalışmada araç plaka bölgesi tespiti probleminin çözümüne yönelik YSA mimarisi tasarlanmış ve YAK algoritması ile APKD üzerinde eğitilmiştir. Eğitilen ağın test verilerindeki %98.82 başarımı, APDK üzerinde eğitilen YSA’nın iyi bir genelleme yaptığını ve sentezleme sonuçları, uygulamanın APDK’da sadece %9’luk alan tüketimi ile gerçekleştirilebildiğini göstermiştir.

Keywords

FPGA, YSA, YAK, Kayan Noktalı Sayılar, Plaka Bölge Tespiti

Implementation of ANN Training with Artificial Bee Colony Algorithm for Plate Region Detection Problem on FPGA

Abstract

Recently, evolutionary algorithms with global search feature are frequently used as an alternative to algorithms that require derivative knowledge in Artificial Neural Network (ANN) trainings. In this study, ANN training was carried out on Field Programmable Gate Arrays (FPGA) with the Artificial Bee Colony (ABC) algorithm, one of the evolutionary algorithms. Number format and activation function approach is important in terms of cost, speed and error sensitivity in FPGA-based implementation. In the study, IEEE 754 floating point number format, which has high sensitivity and dynamism features, was chosen. Since the hardware implementation of the exponential function is difficult, a mathematical approach was used in the hardware implementation of the activation function. In the study, ANN architecture was designed to solve the problem of vehicle license plate region detection and trained on FPGA with ABC algorithm. 98.82% success of the trained network in the test data showed that the ANN trained on FPGA made a good generalization and the synthesis results showed that the application could be realized with only 9% area consumption in FPGA.

Keywords

FPGA, ANN, ABC, Floating Point Number, Plate Region Detection

References

• Merchant, S., Peterson, G. & Kong, S. (2006). Intrinsic Embedded Hardware Evolution of Block-based Neural Networks, International Conference on Engineering of Reconfigurable Systems & Algorithms, 26-29 Haziran.
• Karakuzu, C. & Öztürk, S. (2000). A Comparison of fuzzy, neuro and classical control techniques based on an experimental application, Journal of Quafquaz University, 6, 189-198.
• Çavuşlu, M.A., Karakaya, F. & Altun, H. (2008). ÇKA Tipi Yapay Sinir Aği Kullanılarak Plaka Yeri Tespitinin FPGA’da Donanımsal Gerçeklenmesi, Akıllı Sistemlerde Yenilikler ve Uygulamalar Sempozyumu.
• Issa A. H., Humod A.T. & Gitaffa S.A. (2021). Fpga Implementation of Reconfigurable Intelligent Controller for Mobile Robot, Journal of Mechanical Engineering Research and Developments, 44 (1), 254-264.
• Chun-Hsian Huang, (2021). An FPGA-Based Hardware/Software Design Using Binarized Neural Networks for Agricultural Applications: A Case Study, IEEE Access, 9, 26523 - 26531.
• Tobias Schindler; Armin Dietz. (2020). Real-Time Inference of Neural Networks on FPGAs for Motor Control Applications, 10th International Electric Drives Production Conference (EDPC).
• Li, X. & Areibi, S. (2004). A Hardware Software Co-design Approach for Face Recognaiton, 16th International Conference on Microelectronics, 6-8 Aralık.
• Narendra, K. S. & Parthasaraty, K. (1990). Identification and Control of Dynamical Systems Using Neural Network, IEEE Transactions on Neural Networkworks, 1, 4-27.
• Economou, G.P.K., Mariatos, E.P. Economopoulos, N.M., Lymberopoulos, D. & Goutis, C.E. (1994). FPGA implementation of artificial neural networks: an application on medical expert systems, Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems.
• Mandal, S. K., Sural, S. & Patra, A. (2008). ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 27(1), 188-192.
• Ferrari, S. & Jensenius, M. (2008). A constrained optimization approach to preserving prior knowledge during incremental training, IEEE Trans. Neural Netw., 19(6), 996–1009.
• Wilamowski, B. & M., Chen, Y.(1999). Efficient algorithm for training neural networks with one hidden layer”, International Joint Conference on Neural Networks, 3, 1725-1728.
• Karaboga, D. (2007). Artificial Bee Colony (ABC) Algorithm on Training Artificial Neural Networks, IEEE 15th Signal Processing and Communications Applications, 1 – 4.
• Karaboga, D. Akay, B. V. & Öztürk, C. (2007). Artificial Bee Colony (ABC) Optimization Algorithm For Training Feed-Forward Neural Networks, 4th International Conference Modeling Decisions for Artificial Intelligence, 318-319.
• Kumbhar, P. Y. & Krishnan, S. (2011). Use Of Artificial Bee Colony (ABC) Algorithm in Artificial Neural Network Synthesis, International Journal of Advanced Engineerıng Sciences And Technologies, 11(1), 162 – 171.
• Şahin, S. & Çavuşlu M. A. (2018). FPGA Implementation of Wavelet Neural Network Training with PSO/iPSO, Journal of Circuits, Systems and Computers, 27(6)
• Li, Y. & Chen, X. (2006). A New Stochastic PSO Technique for Neural Network Training, International Symposium on Neural Networks, 564-569.
• Vilovic, I., Burum, N. & Milic, D. (2009). Using particle swarm optimization in training neural network for indoor field strength prediction, International Symposium ELMAR, 275 – 278.
• Martinez, J., Toledo, F.J., Fernandez, E. & Ferrandez, J.M. (2008). A retinomorphic architecture based on discrete-time cellular neural networks using reconfigurable computing, Neurocomputing, 71(4-6), 766-775
• Krips, M., Lammert, T. & Kummert, A. (2002). FPGA implementation of a neural network for a real-time handtracking system, The First IEEE International Workshop on Electronic Design, Test and Applications, 313 – 317.
• Ossoinig, H., Reisinger, E., Steger, C. & Weiss, R. (1996). Design and FPGA-Implementation of a Neural Network, 7th International Conference on signal Processing Applications and Technology, 939-943.
• Zhang, L. (2017). Artificial Neural Network Model Design and Topology Analysis for FPGA Implementation of Lorenz Chaotic Generator, IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)
• Sahin, S., Becerikli, Y. & Yazici, S. (2006). Neural Network Implementation in Hardware Using FPGAs, Lecture Notes in Computer Science 4234, 1105-112.
• Mousa, M., Areibi, S. ve Nichols, K. (2006). On the Arithmetic Precision for Implementing Back-Propagation Networks on FPGA: A Case Study, FPGA Implementations of Neural Networks, 37-61.
• Nedjah, N., Silva, R.M.D., Mourelle, L.M.M. & Silva, M.V.C.D. (2009). Dynamic MAC-based architecture of artificial neural networks suitable for hardware implementation on FPGAs, Neurocomputing, 72(10-12), 2171-2179.
• Ferreira, P., Ribeiro, P., Antunes, A. & Dias, F.M. (2006). A high bit resolution FPGA implementation of a FNN with a new algorithm for the activation function, Neurocomputing, 71(1-3), 71-77.
• Won, E. (2007). A hardware implementation of articial neural nertworks using field programmable gate arrays, Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 581(3), 816-820.
• Li, Z., Huang Y. & Lin W. (2017). FPGA implementation of neuron block for artificial neural network, International Conference on Electron Devices and Solid-State Circuits (EDSSC)
• Ferrer, D., Gonzalez, R., Fleitas, R., Acle, J.P. & Canetti, R. (2004). NeuroFPGA - Implementing Artificial Neural Networks on Programmable Logic Devices, Design, Automation and Test in Europe Conference and Exhibition, s, 218-223.
• Sarić R., Jokić D., Beganović N., Pokvić L.G. & Badnjevi A. (2020), FPGA-based real-time epileptic seizure classification using Artificial Neural Network, Biomedical Signal Processing and Control, 62
• Çavuşlu, M.A., Karakuzu, C. & Şahin, S. (2006). Neural Networkwork Hardware Implementation Using FPGA, 3rd International Symposium on Electrical, Electronic and Computer Engineering Symposium Proceedings, 287-290.
• Savich, A.W., Moussa, M. & Areibi,S. (2007) The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study, IEEE Transactions on Neural Networks, 18(1), 240 – 252
• Çavuşlu, M. A., Karakuzu, C., Şahin, S. & Yakut, M. (2011). Neural Network Training Based on FPGA with Floating Point Number Format and It’s Performance, Neural Computing and Applications, 20(2), 195-202.
• Farmahini-Farahani, A., Fakhraie, S. M. & Safari, S. (2008). Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence, Design, Automation and Test in Europe Conf., 1340-1345.
• Liu, Q., Liu, J., Sang R., Li J., Zhang T. & Zhang, Q. (2018). Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(8), 1575 – 1579.
• Çavuşlu M. A. & Şahin S. (2018). FPGA Implementation of ANN Training using Levenberg and Marquardt Algorithm, Neural Network World, 28(2), 161-178.
• Çavuşlu, M. A., Karakuzu, C. & Karakaya, F. (2012). Neural Identification of Dynamic Systems on FPGA with PSO Learning, Applied Soft Computing, 12(9), 2707–2718.
• Haykın, S. (1999). Neural Networks A Comprehensive Foundation, Prentice Hall Publishing, New Jersey 07458, USA,
• Yu, X. & Deni D. (1999). Implementing Neural Networks In FPGAs, The Institution of Electrical Engineers, London WC2R 0BL, UK.
• Öztemel, E. (2003). Yapay Sinir Ağları, Papatya Yayıncılık.
• Karaboga, D. (2005). An Idea Based On Honey Bee Swarm For Numerıcal Optımızatıon, Technıcal Report-Tr06,Erciyes University, Engineering Faculty, Computer Engineering Department
• Akay, B. & Karaboga, D. (2009). Parameter Tuning for the Artificial Bee Colony Algorithm, 1st International Conference on Computational Collective Intelligence - Semantic Web, Social Networks & Multiagent Systems.
• Elliot, D. L. (1993). A Better Activation Function for Artificial Neural Networks, Technical Research Report T.R. 93-8, Institute for Systems Research, University of Maryland.
• Brysbaert, M. (1991). Algorithms for randomness in the behavioral sciences: A tutorial, Behavior Research Methods, Instruments & Computers, 23, 45-60.