Random Forest Algoritmasının FPGA Üzerinde Gerçekleştirilerek Performans Analizinin Yapılması

Abstract

Random Forest (RF), rastgele oluşturulmuş birden çok karar ağacının çıktısını birleştiren, regresyon ve sınıflandırma problemlerini çözmek için kullanılan bir makine öğrenme algoritmasıdır. RF algoritması, karar ağaçlarının tahminlerinden yola çıkarak sonuca ulaşmayı sağlar. Ormandaki ağaç sayısının artması algoritma sonucunun kesinliğini arttırır. RF algoritması ormandaki karar ağaçları üzerinde rastgele ve sürekli olarak işlem gerçekleştirdiği için paralel mimaride platformlar üzerinde çalıştırılması ile olumlu sonuçlar elde edilebilir. Field Programmable Gate Array (FPGA) entegre devreler, paralel işlem yapabilme yeteneğine sahip olduğundan, RF algoritmasının donanım üzerinde gerçekleştirilen uygulamalarında kullanılması performansı arttırmaktadır. Gerçekleştirilen çalışmada RF algoritması sayısal bir veri seti ile hem MATLAB üzerinde hem de FPGA üzerinde çalıştırılarak sınıflandırma işlemleri gerçekleştirilmiştir. Algoritmadaki işlem modüllerinin ve tüm mantıksal tasarımların geliştirilmesi aşamalarında Very High Speed Integrated Circuit Hardware Description Language (VHDL) kullanılmıştır. VHDL ile oluşturulan tüm tasarımlar Xilinx ISE geliştirme ortamında gerçekleştirilmiştir. Bilgisayar işlemcisi üzerinde MATLAB kullanılarak çalıştırılan ve FPGA mimarisi üzerinde çalıştırılan RF algoritmasının performans, doğruluk ve bellek kullanım oranları açısından karşılaştırmaları yapılarak elde edilen sonuçlar incelenmiştir. Gerçekleştirilen çalışma sonucunda, RF gibi yoğun işlemler ve hesaplamalar yürüten uygulamalarda FPGA kullanımının performans ve bellek kullanımı yönünden bilgisayar işlemcilerine kıyasla yüksek oranda başarı sağladığı görülmüştür.

Keywords

• Random Forest
• FPGA
• VHDL
• Donanım Gerçekleme
• Performans Analizi

Performing Performance Analysis by Implementing Random Forest Algorithm on FPGA

Abstract

Random Forest (RF) is a machine learning algorithm used to solve regression and classification problems, combining the output of multiple randomly generated decision trees. The RF algorithm provides to reach the result based on the predictions of the decision trees. Increasing the number of trees in the forest increases the accuracy of the algorithm result. Since the RF algorithm performs random and continuous operations on the decision trees in the forest, positive results can be obtained by running it on platforms in parallel architecture. Because of Field Programmable Gate Array (FPGA) integrated circuits have the ability to perform parallel operations, the use of the RF algorithm in hardware-based applications increases performance. In this study, classification processes were carried out by running the RF algorithm on both MATLAB and FPGA with a numerical data set. Very High Speed Integrated Circuit Hardware Description Language (VHDL) was used in the development of the processing modules and all logical designs in the algorithm. All designs created with VHDL were carried out in the Xilinx ISE development environment. The results obtained by comparing the performance, accuracy and memory usage rates of the RF algorithm, which is run on the computer processor using MATLAB and run on the FPGA architecture, are examined. As a result of the study, it has been seen that the use of FPGAs in applications that carry out intensive operations and calculations such as RF provides a higher success rate compared to computer processors in terms of performance and memory usage.

Keywords

• Random Forest
• FPGA
• VHDL
• Hardware Realization
• Performance Analysis

References

1. [1]. Cheng, C., Bouganis, C. S., Accelerating random forest training process using FPGA, 23rd International Conference on Field programmable Logic and Applications, 2013, 1-7, IEEE.
2. [2]. Caruana, R., Niculescu-Mizil, A., An empirical comparison of supervised learning algorithms, In Proceedings of the 23rd international conference on Machine learning, 2006, 161-168.
3. [3]. Freund, Y. Schapire, R., Experiments with a new boosting algorithm, Machine Learning: Proceedings of the Thirteenth International Conference, 1996, 148–156.
4. [4]. Amit, Y., Geman, D., Shape quantization and recognition with randomized trees, Neural computation, 1997, 9(7), 1545-1588.
5. [5]. Breiman, L., Random forests. Machine learning, 2001, 45(1), 5-32.
6. [6]. Lin, X., College student employment data platform based on FPGA and machine learning, Microprocessors and Microsystems, 2020, 103471.
7. [7]. Leilei, W., Huina, C., Physical education image analysis based on virtual crowd simulation and FPGA, Microprocessors and Microsystems, 2020, 79, 103319.
8. [8]. Zhang, Z., Semi-supervised hyperspectral image classification algorithm based on graph embedding and discriminative spatial information, Microprocessors and Microsystems, 2020, 75, 103070.

9. [9]. Devika, K. N., Bhakthavatchalu, R., Design of reconfigurable LFSR for VLSI IC testing in ASIC and FPGA, International conference on communication and signal processing (ICCSP), 2017, 0928-0932, IEEE.
10. [10]. Vannal, N. S., Siddamal, S. V., Bidaralli, S. V., Bhille, M. S., Design and testing of combinational Logic circuits using built in self test scheme for FPGAs, Fifth international conference on communication systems and network technologies, 2015, 903-907, IEEE.
11. [11]. Bhakthavatchalu, R., Krishnan, S., Vineeth, V., Devi, M. N., Deterministic seed selection and pattern reduction in Logic BIST, In 18th International Symposium on VLSI Design and Test, 2014, 1-2, IEEE.
12. [12]. Panda, A. K., Rajput, P., Shukla, B., FPGA implementation of 8, 16 and 32 bit LFSR with maximum length feedback polynomial using VHDL, International Conference on Communication Systems and Network Technologies, 2012, 769-773, IEEE.
13. [13]. J. Salamon, C. Jacoby and J. P. Bello, A Dataset and Taxonomy for Urban Sound Research, 22nd ACM International Conference on Multimedia, Orlando USA, 2014.
14. [14]. Teng, Z., Chu, L., Chen, K., He, G., Fu, Y., Li, L., Hardware Implementation of Random Forest Algorithm Based on Classification and Regression Tree, IEEE International Conference on Information Technology, Big Data and Artificial Intelligence (ICIBA), 2020, 1422-1427, IEEE.
15. [15]. Van Essen, B., Macaraeg, C., Gokhale, M., Prenger, R., Accelerating a random forest classifier: Multi-core, GP-GPU, or FPGA?, IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, 2012, 232-239, IEEE.
16. [16]. Lin, X., Blanton, R. S., Thomas, D. E., Random forest architectures on FPGA for multiple applications, In Proceedings of the on Great Lakes Symposium on VLSI, 2017, 415-418.
17. [17]. Jinguji, A., Sato, S., Nakahara, H., An FPGA realization of a random forest with k-means clustering using a high-level synthesis design, IEICE TRANSACTIONS on Information and Systems, 2018, 101(2), 354-362.
18. [18]. Mametjanov, A., Balaprakash, P., Choudary, C., Hovland, P. D., Wild, S. M., Sabin, G., Autotuning FPGA design parameters for performance and power, IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, 2015, 84-91, IEEE.
19. [19]. Biau, G., Scornet, E., A random forest guided tour, 2016, Test, 25(2), 197-227.
20. [20]. Ali, A. B. W., Prediction of Employee Turn Over Using Random Forest Classifier with Intensive Optimized Pca Algorithm, Wireless Personal Communications, 2021, 1-18.