Low-Error Reconfigurable Fixed-Width Multiplier for Image Processing Applications

Year 2020, Volume: 33 Issue: 1, 90 - 104, 01.03.2020

Sivanantham S Jean Jenifer Nesam Jeyakumar

https://doi.org/10.35378/gujs.434806

Abstract

Compensating the error using additional circuitry is mandatory in a low-error fixed-width multiplier. Instead of compensating the error, reconfiguring n-bit fixed-width multiplier to n/2-bit error-free full-width multiplier using decomposed multiplication is proposed in this paper. The decomposed block multiplication using an area-efficient New Bit Pair Recoding (NBPR) algorithm in fixed-width mode shows a relatively lesser truncation error than existing truncated multipliers. Reconfigurable 16x16   NBPR multiplier in three different modes (8x8, 16x8,16x16) with a fixed 16-bit product is verified on the TSMC 65nm CMOS standard cell library. The experimental results show that the NBPR multiplier consumes a lesser area than standard Booth multipliers. Evaluating the proposed multiplier in imaging shows improved PSNR with minimal error compared to other fixed-width multipliers

Keywords

Reconfigurable multiplier, Fixed-Width multiplier, NBPR algorithm, Image processing applications

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