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Year 2023, Volume: 36 Issue: 1, 249 - 261, 01.03.2023
https://doi.org/10.35378/gujs.937858

Abstract

References

  • [1] Landaurer, R., “Irreversibility and heat generation in the computational process”, IBM, Journal of Research and Development, 5: 183–191, (1961).
  • [2] Bennett, C.H., “Logical reversibility of computation”, IBM Journal of. Research and Development, 17: 525–532, (1973).
  • [3] Parate, P. G., Patil, P.S., Subbaraman, S., “ASIC implementation of 4-bit multipliers”, In Emerging Trends in Engineering and Technology, ICETET'08, IEEE: 408-413, (2008).
  • [4] Thapliyal, H., Arabnia, H.R., “A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics”, ESA/VLSI: 440-446, (2004).
  • [5] Mano, M. M., “Computer System Architecture”, 3rd edition, PHI: 346- 347, (1993).
  • [6] Kerntopf, P., Perkowski, M.A., Khan, M.H.A., “On the universality of general reversible multiple valued logic gates”, IEEE Proceeding of the 34th international symposium on multiple valued logic (ISMVL'04): 68-73, (2004).
  • [7] Shams, M., Haghparast, M., Navi, K., “Novel Reversible Multiplier Circuit in nanotechnology”, World Applied Science Journal, 3(5): 806-810, (2008).
  • [8] Naderpour, F., Vafaei, A., “Reversible Multipliers: Decreasing the Depth of the Circuit” International Conference on Energy Conservation and Efficiency ICECE, (2008).
  • [9] Ehsanpour, M., Moallem, P., Vafaei, A., “Design of a Novel Reversible multiplier Circuit Using Modified Full Adder”, International Conference on Computer Design and Applications, ICCDA 1389, (2010).
  • [10] Islam, M.S., Rahman, M.M., Begum, Z., Hafiz, M.Z., “Low-cost quantum realization of reversible multiplier circuit”, Information Technology Journal, 8(2): 208-213, ISSN 1812-5638, (2009).
  • [11] Thapliyal, H., Ranganathan, N., “Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits”, ACM Journal on Emerging Technologies in Computing Systems, (2017).
  • [12] Hemalatha, K.N., Sangeetha, B.G., “Performance Analysis of array multiplier using reversible logic”, International Conference on Microelectronics Computing & Communication Systems, (2020).
  • [13] Poornima, M., Suma, M.S., Namita Palecha., Malavika, T., “Fault-Tolerant Reversible Logic for Combinational Circuits: A Survey", Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking, Springer, (2013).
  • [14] Rangaraju, H.G., Aakashbabu Suresh., Muralidhara, K.N., “Design of Efficient Reversible Multiplier”, Advances in Computing & Inf. Technology, AISC 178: 571–579, Springer, (2013).
  • [15] Mojtaba V., “Novel parity-preserving reversible logic array multipliers”, Published online, The journal of Superconducting, Springer, (2017).
  • [16] Radha, N., Maheswari, M., “High Speed Efficient Multiplier Design using Reversible Gates", International Conference on Computer Communication and Informatics (ICCCI): 04-06, (2018).
  • [17] Hemalatha, K.N., Sangeetha, B. G.,” Ultra-Optimized 8-bit Unsigned Array Multiplier design using Reversible Logic”, GIS Science Journal, ISSN NO: 1869-9391: 1105-1110, (2021).
  • [18] Ratnababu, Y., Syamala, Y., “Implementation and testing of multipliers using reversible logic”, Proceedings of International Conference on Advances in Recent Technologies in Communication and Computing, (2011).
  • [19] Rajmohan, V., Umamaheswari, O., “Design of Compact Baugh-Wooley Multiplier Using Reversible Logic”, Circuits and Systems, Scientific Research Publishing, 7: 1522-1529, (2016).
  • [20] Moshnyaga, V.G., Tamaru, K., “The comparative study of switching activity reduction techniques for design of low power multipliers”, International Symposium on Circuits and Systems (ISCAS), (1995).
  • [21] Yan, J., Chen, Z., “Low-Power Multiplier Design with Row and Column Bypassing”, IEEE International SOC Conference, (2009).
  • [22] Bhagyalakshmi, H.R., Venkatesha, M.K., “An Improved Design of a Multiplier Using Reversible Logic Gates”, International Journal on Engineering Science and Technology, 2: 3838-3845, (2010).
  • [23] Haghparast, M., Jassbi, S.J., Navi, K., Hashemipour, O., “Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology”, World Applied Sciences Journal, 3: 974-978, (2008).
  • [24] Islam, M.S., Rahman, M.M., Begum, Z., Hafiz, M.Z., “Low-Cost Quantum Realization of Reversible Multiplier Circuit”, Information Technology Journal, 8: 208-213, (2009).
  • [25] Haghparast, M., Jassbi, S. J., Navi, K., Hashemipour, O., “Design of a Novel Reversible Multiplier Circuit using HNG Gate in Nanotechnology”, World Applied Sciences Journal, 10: 974-978, (2008).
  • [26] Kumar, P., Kumar Sharma, R., “Low power multiplier design with improved column bypassing scheme”, Electrical and Electronics Engineering: An International Journal (ELELIJ), 5, (2016).
  • [27] Jigalur, V., Meharunnis, S. P., “Efficient reversible multiplier using column bypass technique for dsp applications”, International Journal of Engineering Research and General Science, 3(1): (2015).
  • [28] Saligram, R., Rakshith, T.R., “Design of reversible multipliers for linear filtering applications in DSP”, International Journal of VLSI design & Communication Systems (VLSICS), 3, (2012).
  • [29] Booth, A.D., “A signed binary multiplication technique”, The Quarterly Journal of Mechanics and Applied Mathematics, 4(2): 236–240, (1951).
  • [30] Weste, N.H.E., Harris, D.M., “Cmos VLSI Design: A Circuits and Systems Perspective”, 3/E. Pearson Education India, chapter- Datapath Subsystems, (2006).
  • [31] Sultana, J., Mitra, S., Chowdhury, A.R., “On the Analysis of Reversible Booth’s Multiplier”, 28th International Conference on VLSI Design and 14th International Conference on Embedded Systems, IEEE, (2015).
  • [32] Nandal, A., Vigneswaran, T., Rana, A.K., “Booth Multiplier using Reversible Logic with Low Power and Reduced Logical Complexity”, Indian Journal of Science and Technology, 7(4): 525–529, (2014).
  • [33] Talawar, K., Hosamani, P., “Ultra Area Efficient Reversible Quantum Radix-2 Booth’s Recoding Multiplier for Low Power Applications”, IEEE, (2014).
  • [34] Rahman, M., Hossain, M., Jamal., L., Nowrin, S., “Designing of a reversible fault tolerant booth multiplier”, Bangladesh Journal of Scientific and Industrial Research, (2018).
  • [35] Nagamani, A. N., Nikhil, R., Nagaraj, M., Agrawal, V.K., “Reversible Radix-4 Booth Multiplier for DSP Applications”, IEEE, (2016).
  • [36] Vamsi, H.S.R., Reddy, K. S., Babu, C., Murty, N. S., “Design of reversible logic based 32-bit MAC unit using radix-16 booth encoded Wallace tree multiplier”, International Conference on Computer Communication and Informatics, IEEE, (2018).
  • [37] Gowthami, P., Satyanarayana, R.V.S., “Performance evaluation of reversible Vedic multiplier”, ARPN Journal of Engineering and Applied Sciences, (2018).
  • [38] Ariafar, Z., Mosleh, M., “Effective Designs of Reversible Vedic Multiplier”, International Journal of Theoretical Physics, Springer, (2019).
  • [39] Radha, N., Maheswari, M., “An energy efficient multiplier using reversible gates”, Journal of Physics: Conference Series, IOP Publishing, (2020).
  • [40] Rashno, M., Haghparast, M., Mosleh, M., “A new design of a low-power reversible Vedic multiplier”, International Journal of Quantum Information, World Scientific Publishing, (2020).
  • [41] Lakshmi, G.S., Fatima, K., Madhavi, B.K., “Compressor based 8x8 bit Vedic multiplier using reversible logic”, IEEE, (2016).
  • [42] Ravi, J.N., Vijay Prakash, A.M., Madan, S., “Design and Implementation of Vedic Multipliers Using Reversible Logic Gates”, Journal of Electrical & Electronic Systems, (2018).
  • [43] Lakshmi, K., Kumar, S., Rao, R., “Implementation of Vedic multiplier using reversible gates”, CNDC, (2015).

State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing

Year 2023, Volume: 36 Issue: 1, 249 - 261, 01.03.2023
https://doi.org/10.35378/gujs.937858

Abstract

Multiplication is the key crucial operation in realizing digital signal processing (DSP) functions. It is accomplished by using diverse multiplier architectures. Multiplication operation is furthermost basic and normally used action in the central processing unit (CPU). The multiplication operation is the most fundamental and commonly performed activity in the central processing unit (CPU). An efficient multiplier design should have a high speed, small area, and a low power consumption. Compact, efficient multipliers with minimal power dissipation are needed. The proposed paper provides a thorough inspection of multipliers such as the Array multiplier, Booth multiplier, column bypass multiplier, Baugh-Wooley multiplier, and Vedic multiplier based on their operational activities and working, as well as their benefits and limits. A comparison of these multipliers' performance parameters such as speed, area, power consumption, quantum cost, garbage generation and circuit complexity.

References

  • [1] Landaurer, R., “Irreversibility and heat generation in the computational process”, IBM, Journal of Research and Development, 5: 183–191, (1961).
  • [2] Bennett, C.H., “Logical reversibility of computation”, IBM Journal of. Research and Development, 17: 525–532, (1973).
  • [3] Parate, P. G., Patil, P.S., Subbaraman, S., “ASIC implementation of 4-bit multipliers”, In Emerging Trends in Engineering and Technology, ICETET'08, IEEE: 408-413, (2008).
  • [4] Thapliyal, H., Arabnia, H.R., “A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics”, ESA/VLSI: 440-446, (2004).
  • [5] Mano, M. M., “Computer System Architecture”, 3rd edition, PHI: 346- 347, (1993).
  • [6] Kerntopf, P., Perkowski, M.A., Khan, M.H.A., “On the universality of general reversible multiple valued logic gates”, IEEE Proceeding of the 34th international symposium on multiple valued logic (ISMVL'04): 68-73, (2004).
  • [7] Shams, M., Haghparast, M., Navi, K., “Novel Reversible Multiplier Circuit in nanotechnology”, World Applied Science Journal, 3(5): 806-810, (2008).
  • [8] Naderpour, F., Vafaei, A., “Reversible Multipliers: Decreasing the Depth of the Circuit” International Conference on Energy Conservation and Efficiency ICECE, (2008).
  • [9] Ehsanpour, M., Moallem, P., Vafaei, A., “Design of a Novel Reversible multiplier Circuit Using Modified Full Adder”, International Conference on Computer Design and Applications, ICCDA 1389, (2010).
  • [10] Islam, M.S., Rahman, M.M., Begum, Z., Hafiz, M.Z., “Low-cost quantum realization of reversible multiplier circuit”, Information Technology Journal, 8(2): 208-213, ISSN 1812-5638, (2009).
  • [11] Thapliyal, H., Ranganathan, N., “Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits”, ACM Journal on Emerging Technologies in Computing Systems, (2017).
  • [12] Hemalatha, K.N., Sangeetha, B.G., “Performance Analysis of array multiplier using reversible logic”, International Conference on Microelectronics Computing & Communication Systems, (2020).
  • [13] Poornima, M., Suma, M.S., Namita Palecha., Malavika, T., “Fault-Tolerant Reversible Logic for Combinational Circuits: A Survey", Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking, Springer, (2013).
  • [14] Rangaraju, H.G., Aakashbabu Suresh., Muralidhara, K.N., “Design of Efficient Reversible Multiplier”, Advances in Computing & Inf. Technology, AISC 178: 571–579, Springer, (2013).
  • [15] Mojtaba V., “Novel parity-preserving reversible logic array multipliers”, Published online, The journal of Superconducting, Springer, (2017).
  • [16] Radha, N., Maheswari, M., “High Speed Efficient Multiplier Design using Reversible Gates", International Conference on Computer Communication and Informatics (ICCCI): 04-06, (2018).
  • [17] Hemalatha, K.N., Sangeetha, B. G.,” Ultra-Optimized 8-bit Unsigned Array Multiplier design using Reversible Logic”, GIS Science Journal, ISSN NO: 1869-9391: 1105-1110, (2021).
  • [18] Ratnababu, Y., Syamala, Y., “Implementation and testing of multipliers using reversible logic”, Proceedings of International Conference on Advances in Recent Technologies in Communication and Computing, (2011).
  • [19] Rajmohan, V., Umamaheswari, O., “Design of Compact Baugh-Wooley Multiplier Using Reversible Logic”, Circuits and Systems, Scientific Research Publishing, 7: 1522-1529, (2016).
  • [20] Moshnyaga, V.G., Tamaru, K., “The comparative study of switching activity reduction techniques for design of low power multipliers”, International Symposium on Circuits and Systems (ISCAS), (1995).
  • [21] Yan, J., Chen, Z., “Low-Power Multiplier Design with Row and Column Bypassing”, IEEE International SOC Conference, (2009).
  • [22] Bhagyalakshmi, H.R., Venkatesha, M.K., “An Improved Design of a Multiplier Using Reversible Logic Gates”, International Journal on Engineering Science and Technology, 2: 3838-3845, (2010).
  • [23] Haghparast, M., Jassbi, S.J., Navi, K., Hashemipour, O., “Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology”, World Applied Sciences Journal, 3: 974-978, (2008).
  • [24] Islam, M.S., Rahman, M.M., Begum, Z., Hafiz, M.Z., “Low-Cost Quantum Realization of Reversible Multiplier Circuit”, Information Technology Journal, 8: 208-213, (2009).
  • [25] Haghparast, M., Jassbi, S. J., Navi, K., Hashemipour, O., “Design of a Novel Reversible Multiplier Circuit using HNG Gate in Nanotechnology”, World Applied Sciences Journal, 10: 974-978, (2008).
  • [26] Kumar, P., Kumar Sharma, R., “Low power multiplier design with improved column bypassing scheme”, Electrical and Electronics Engineering: An International Journal (ELELIJ), 5, (2016).
  • [27] Jigalur, V., Meharunnis, S. P., “Efficient reversible multiplier using column bypass technique for dsp applications”, International Journal of Engineering Research and General Science, 3(1): (2015).
  • [28] Saligram, R., Rakshith, T.R., “Design of reversible multipliers for linear filtering applications in DSP”, International Journal of VLSI design & Communication Systems (VLSICS), 3, (2012).
  • [29] Booth, A.D., “A signed binary multiplication technique”, The Quarterly Journal of Mechanics and Applied Mathematics, 4(2): 236–240, (1951).
  • [30] Weste, N.H.E., Harris, D.M., “Cmos VLSI Design: A Circuits and Systems Perspective”, 3/E. Pearson Education India, chapter- Datapath Subsystems, (2006).
  • [31] Sultana, J., Mitra, S., Chowdhury, A.R., “On the Analysis of Reversible Booth’s Multiplier”, 28th International Conference on VLSI Design and 14th International Conference on Embedded Systems, IEEE, (2015).
  • [32] Nandal, A., Vigneswaran, T., Rana, A.K., “Booth Multiplier using Reversible Logic with Low Power and Reduced Logical Complexity”, Indian Journal of Science and Technology, 7(4): 525–529, (2014).
  • [33] Talawar, K., Hosamani, P., “Ultra Area Efficient Reversible Quantum Radix-2 Booth’s Recoding Multiplier for Low Power Applications”, IEEE, (2014).
  • [34] Rahman, M., Hossain, M., Jamal., L., Nowrin, S., “Designing of a reversible fault tolerant booth multiplier”, Bangladesh Journal of Scientific and Industrial Research, (2018).
  • [35] Nagamani, A. N., Nikhil, R., Nagaraj, M., Agrawal, V.K., “Reversible Radix-4 Booth Multiplier for DSP Applications”, IEEE, (2016).
  • [36] Vamsi, H.S.R., Reddy, K. S., Babu, C., Murty, N. S., “Design of reversible logic based 32-bit MAC unit using radix-16 booth encoded Wallace tree multiplier”, International Conference on Computer Communication and Informatics, IEEE, (2018).
  • [37] Gowthami, P., Satyanarayana, R.V.S., “Performance evaluation of reversible Vedic multiplier”, ARPN Journal of Engineering and Applied Sciences, (2018).
  • [38] Ariafar, Z., Mosleh, M., “Effective Designs of Reversible Vedic Multiplier”, International Journal of Theoretical Physics, Springer, (2019).
  • [39] Radha, N., Maheswari, M., “An energy efficient multiplier using reversible gates”, Journal of Physics: Conference Series, IOP Publishing, (2020).
  • [40] Rashno, M., Haghparast, M., Mosleh, M., “A new design of a low-power reversible Vedic multiplier”, International Journal of Quantum Information, World Scientific Publishing, (2020).
  • [41] Lakshmi, G.S., Fatima, K., Madhavi, B.K., “Compressor based 8x8 bit Vedic multiplier using reversible logic”, IEEE, (2016).
  • [42] Ravi, J.N., Vijay Prakash, A.M., Madan, S., “Design and Implementation of Vedic Multipliers Using Reversible Logic Gates”, Journal of Electrical & Electronic Systems, (2018).
  • [43] Lakshmi, K., Kumar, S., Rao, R., “Implementation of Vedic multiplier using reversible gates”, CNDC, (2015).
There are 43 citations in total.

Details

Primary Language English
Subjects Engineering
Journal Section Electrical & Electronics Engineering
Authors

Hemalatha K N 0000-0003-3551-5517

Sangeetha B G This is me

Publication Date March 1, 2023
Published in Issue Year 2023 Volume: 36 Issue: 1

Cite

APA K N, H., & B G, S. (2023). State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing. Gazi University Journal of Science, 36(1), 249-261. https://doi.org/10.35378/gujs.937858
AMA K N H, B G S. State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing. Gazi University Journal of Science. March 2023;36(1):249-261. doi:10.35378/gujs.937858
Chicago K N, Hemalatha, and Sangeetha B G. “State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing”. Gazi University Journal of Science 36, no. 1 (March 2023): 249-61. https://doi.org/10.35378/gujs.937858.
EndNote K N H, B G S (March 1, 2023) State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing. Gazi University Journal of Science 36 1 249–261.
IEEE H. K N and S. B G, “State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing”, Gazi University Journal of Science, vol. 36, no. 1, pp. 249–261, 2023, doi: 10.35378/gujs.937858.
ISNAD K N, Hemalatha - B G, Sangeetha. “State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing”. Gazi University Journal of Science 36/1 (March 2023), 249-261. https://doi.org/10.35378/gujs.937858.
JAMA K N H, B G S. State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing. Gazi University Journal of Science. 2023;36:249–261.
MLA K N, Hemalatha and Sangeetha B G. “State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing”. Gazi University Journal of Science, vol. 36, no. 1, 2023, pp. 249-61, doi:10.35378/gujs.937858.
Vancouver K N H, B G S. State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing. Gazi University Journal of Science. 2023;36(1):249-61.