The Short Channel and Quantum Confinement Effects on Transfer Characteristics of Si NWMOSFET Depending on the Gate Length and Temperature

Year 2022, , 692 - 703, 01.06.2022

İbrahim Genç , Semran Ipek

https://doi.org/10.21597/jist.999374

Cited By: 1

Abstract

With advancements in nanomaterial synthesis, semiconductor device technology entered a new era with nanotechnology. In fact, quantum effects such as confinement and tunneling have played a significant role in device characteristics. In this work, we have investigated quantum ballistic transport properties of Si nanowire MOSFET (Si NWMOSFET) with 4 nm gate length. Since gate length is shorter than the electron wavelength in our Si NWMOSFET, ballistic transport in one dimension (1D) is expected to be the dominant mechanism for carrier transport. Therefore, the parameters which are crucial for efficient MOSFET operation such as gate length, temperature, gate voltage have been simulated using the density gradient method to present quantum confinement effect on device transfer characteristics. We have found that Si NWMOSFET has an I_on/I_off ratio > 10^8, which is close to ideal value for similar nano MOSFETs. Moreover, due to short channel, intersubband scattering can deteriorate 1D ballistic transport properties of Si NWMOSFET, especially in low temperatures.

Keywords

Si NWMOSFET, ballistic transport, 1D transport, short channel effect, quantum confinement

Project Number

FB169

References

• Ancona MG, 2011. Density-gradient theory: A macroscopic approach to quantum confinement and tunneling in semiconductor devices. Journal of Computational Electronics, 10(1–2), 65–97.
• Bangsaruntip S, Cohen GM, Majumdar A, Zhang Y, Engelmann SU, Fuller NCM, Gignac LM, Mittal S, Newbury JS, Guillorn M, Barwicz T, Sekaric L, Frank MM, Sleight JW, 2009. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling. 2009 IEEE International Electron Devices Meeting (IEDM), 1–4.
• Bollani M, Salvalaglio M, Benali A, Bouabdellaoui M, Naffouti M, Lodari M, Corato S, Fedorov A, Voigt A, Fraj I, Favre L, Claude J, Grosso D, Nicotra G, Mio A, Ronda A, Berbezier I, Abbarchi M, 2019. Templated dewetting of single-crystal sub-millimeter-long nanowires and on-chip silicon circuits”, Nature Communications, 10(1): 5632.
• Buin AK, Verma A, Svizhenko A, Anantram MP, 2008. Significant Enhancement of Hole Mobility in [110] Silicon Nanowires Compared to Electrons and Bulk Silicon. Nano Letters, 8(2): 760–765.
• Chhowalla M Jena, D, ZhangH, 2016. Two-dimensional semiconductors for transistors. https://doi.org/10.1038/natrevmats2016.52
• Cho KH, Yeo KH, Yeoh YY, Suk SD, Li M, Lee JM, Kim MS, Kim DW, Park D, Hong BH, Jung Y, Hwang SW, 2008. Experimental evidence of ballistic transport in cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field-effect transistors. Applied Physics Letters, 92(5): 052102.
• Colinge JP, (2004). Multiple-gate SOI MOSFETs. Solid-State Electronics, 48(6): 897–905.
• Ferain I, Colinge CA, Colinge JP, 2011. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature, 479(7373): 310–316.
• Jin S, Fischetti Mv, Tang T, 2007. Modeling of electron mobility in gated silicon nanowires at room temperature: Surface roughness scattering, dielectric screening, and band nonparabolicity. Journal of Applied Physics, 102(8): 83715.
• Jönsson A, Svensson J, Fiordaliso E, Lind E, Hellenbrand M, Wernersson L, 2021. Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance. ACS Applied Electronic Materials, 3(12): 5240-5247.
• Jung HE, Shin M, 2013. Surface-Roughness-Limited Mean Free Path in Si Nanowire FETs. http://arxiv.org/abs/1304.5597
• Kim R, Lundstrom MS, 2008. Characteristic features of 1-D ballistic transport in nanowire MOSFETs. IEEE Transactions on Nanotechnology, 7(6): 787–794.
• Li Z, Chen Y, Li X, Kamins TI, Nauka K, Williams RS, 2004. Sequence-Specific Label-Free DNA Sensors Based on Silicon Nanowires. Nano Letters, 4(2): 245–247.
• Lim D, Kim M, Kim Y, Kim S, 2017. Memory characteristics of silicon nanowire transistors generated by weak impact ionization. Scientific Reports, 7(1): 12436.
• Luisier M, Klimeck G, 2010. Simulation of nanowire tunneling transistors: From the Wentzel–Kramers–Brillouin approximation to full-band phonon-assisted tunneling. Journal of Applied Physics, 107(8): 084507.
• Luisier M, Schenk A, Fichtner W, Klimeck G, 2006. Atomistic simulation of nanowires in the sp3d5s* tight-binding formalism: From boundary conditions to strain calculations. Physical Review B, 74(20): 205323.
• Nair PR, Alam MA, 2007. Design Considerations of Silicon Nanowire Biosensors. IEEE Transactions on Electron Devices, 54(12): 3400–3408.
• Nehari K, Cavassilas N, Autran JL, Bescond M, Munteanu D, Lannoo M, (2005). Influence of Band-Structure on Electron Ballistic Transport in Silicon Nanowire MOSFET’s: an Atomistic Study, in Proceedings of 35th European Solid-State Device Research Conference, ESSDERC 2005, 229-232, doi: 10.1109/ESSDER.2005.1546627.
• Neophytou N, Paul A, Klimeck G, 2008. Bandstructure Effects in Silicon Nanowire Hole Transport. IEEE Transactions on Nanotechnology, 7(6): 710–719.
• Neophytou N, Paul A, Lundstrom MS, Klimeck G, 2008. Bandstructure Effects in Silicon Nanowire Electron Transport. IEEE Transactions on Electron Devices, 55(6): 1286–1297.
• Ng RMY, Wang T, Liu F, Zuo X, He J, Chan M, 2009. Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation. IEEE Electron Device Letters, 30(5): 520–522.
• Peng K, Huang Z, Zhu J, 2004. Fabrication of Large-Area Silicon Nanowire p–n Junction Diode Arrays. Advanced Materials, 16(1): 73–76.
• Peng K, Xu Y, Wu Y, Yan Y, Lee ST, Zhu J, 2005. Aligned Single-Crystalline Si Nanowire Arrays for Photovoltaic Applications. Small, 1(11): 1062–1067.
• Singh N, Buddharaju KD, Manhas SK, Agarwal A, Rustagi SC, Lo GQ, Balasubramanian N, Kwong D, 2008. Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications. IEEE Transactions on Electron Devices, 55(11): 3107–3118.
• Singh N, Lim FY, Fang WW, Rustagi SC, Bera LK, Agarwal A, Tung CH, Hoe KM, Omampuliyur SR, Tripathi D, Adeyeye AO, Lo GQ, Balasubramanian N, Kwong DL, 2006. Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance. 2006 International Electron Devices Meeting, 1–4. https://doi.org/10.1109/IEDM.2006.346840
• Stanojević Z, Baumgartner O, Sverdlov V, Kosina H, 2010. Electronic band structure modeling in strained Si-nanowires: Two band k p versus tight binding. 2010 14th International Workshop on Computational Electronics, 1–4. https://doi.org/10.1109/IWCE.2010.5677927
• Thingujam T, Son D, Kim J, Cristoloveanu S, Lee J, 2020. Effects of Interface Traps and Self-Heating on the Performance of GAA GaN Vertical Nanowire MOSFET”, IEEE Transactions on Electron Devices, 67(3): 816-821
• Trivedi K, Yuk H, Floresca HC, Kim MJ, Hu W, 2011. Quantum Confinement Induced Performance Enhancement in Sub-5-nm Lithographic Si Nanowire Transistors. Nano Letters, 11(4): 1412–1417.
• Tsuchiya H, Fujii K, Mori T, Miyoshi T, 2006. A quantum-corrected Monte Carlo study on quasi-ballistic transport in nanoscale MOSFETs. IEEE Transactions on Electron Devices, 53(12): 2965–2971.
• Voisin B, Maurand R, Barraud S, Vinet M, Jehl X, Sanquer M, Renard J, De Franceschi S, 2016. Electrical Control of g-Factor in a Few-Hole Silicon Nanowire MOSFET. Nano Letters, 16(1): 88-92.
• Yi KS, Trivedi K, Floresca HC, Yuk H, Hu W, Kim MJ, 2011. Room-temperature quantum confinement effects in transport properties of ultrathin si nanowire field-effect transistors. Nano Letters, 11(12): 5465–5470.
• Zhang Q, Yin H, Meng L, Yao J, Li J, Wang G, Li Y, Wu Z, Xiong W, Yang H, Tu H, Li J, Zhao C, Wang W, Ye T, 2018. Novel GAA Si Nanowire p-MOSFETs With Excellent Short-Channel Effect Immunity via an Advanced Forming Process. IEEE Electron Device Letters, 39(4): 464-467.
• Zhu H, 2017. Semiconductor Nanowire MOSFETs and Applications, InTech.