Şebeke bağlantılı tek fazlı dokuz seviyeli asimetrik evirici tasarımı ve analizi

Year 2017, Volume: 23 Issue: 5, 512 - 518, 20.10.2017

Ersan Kabalcı Rıdvan Canbaz

Abstract

Günümüzde
yaygın olarak kullanılan çok seviyeli Eviriciler (ÇSE) için giriş tarafındaki
gerilim seviyeleri önemli bir sınırlayıcı olmaktadır. Yüksek güçlü enerji
sistemlerinde, iki seviyeli eviricilerde kullanılacak anahtarlama elemanının
gücünün yetersiz kalması, çıkış dalga şeklinin sinüzoidalden uzak olması ve
düşük gerilim üretilmesinden kaynaklı transformatör kullanılması klasik iki
seviyeli eviricilerin dezavantajlarındandır. Ayrıca iki seviyeli eviricilerde
toplam harmonik distorsiyonunu (THD) azaltmak için yüksek anahtarlama
frekansının kullanılması anahtarlama kayıplarını arttırmaktadır. Bu çalışmada,
asimetrik eviricinin THD oranını düşürmek ve şebeke bağlantısını
gerçekleştirmek için Matlab/Simulink ortamında modelleme yapılmıştır. Çalışma
kapsamında, üçlü besleme gerilimi yapısında asimetrik H-köprü evirici
modellenmiş ve sinüzoidal darbe genişlik modülasyonu (SDGM) kontrol algoritması
ile anahtarlama işaretleri üretilmiştir. Eviricinin şebeke bağlantısı,
geliştirilen PI kontrol algoritması ve PLL kontrol algoritmalarıyla
denetlenmiştir. Tasarlanan PI ile elde edilen sonuçlarda THD oranının düştüğü
görülmektedir. Ayrıca sistemin açık döngüye göre dinamik ve hızlı çalıştığı
gözlemlenmiştir. Sistem hem açık döngü çalıştırılarak hem PI kontrolcü ile hem
de PI-PLL ile çalıştırılarak THD oranları incelenmiş ve önerilen tek fazlı
şebeke etkileşimli evirici kontrol yöntemi doğrulanmıştır. Yapılan çalışmalar
sonucunda sistemin kontrolünde PI ve PI-PLL kontrollerinden elde edilen
sonuçların yaklaşık aynı olduğu ancak PI-PLL kontrol yönteminin daha verimli
sonuçlar sağladığı görülmüştür. Ayrıca, tasarlanan PLL yöntemiyle karışık
kontrol yöntemlerine ve algoritmalara ihtiyaç olmadan sistem şebekeye
bağlanmıştır.

Keywords

Asimetrik evirici, PI kontrolcü, PLL kontrolcü, Güneş enerjisi, Toplam harmonik distorsiyonu

Design and analysis of a grid-tied single phase nine level asymmetrical inverter

Abstract

The supply
voltage levels of the multilevel inverters (MLIs) that are widely used nowadays
are the significant limiting parameters. The major drawbacks of conventional
two-level inverters used in the high power systems are the insufficient switch
power against the power range, non-sinusoidal output waveforms, and increasing
line transformer requirements. Furthermore, the higher switching frequency
requirement to reduce the total harmonic distortion (THD) increases the
switching losses. This study presents the design and analysis of a controller
that is performed by using Matlab/Simulink environment. The asymmetrical MLI
topology is constituted in trinary DC supply structure, and the switching
frequencies are generated in sinusoidal pulse width modulation (SPWM) scheme.
The grid connection of the inverter is controlled by the implemented proportional-integral
(PI) controller and phase locked loop (PLL) control algorithm. The proposed
control method is compared to conventional controllers in terms of THD rates
and observer structure. It is observed that the designed PI controller decreases
the THD ratio, with higher dynamic response. The improved control mechanism is
tested under open-loop, PI controlled, and PI-PLL controlled structures to
determine the THD ratios where the proposed single phase grid-tied control
method is verified. The performed analysis results have shown that the PI and
PI-PLL controllers provide almost same result, but the PI-PLL controller draws
faster dynamic response comparing to PI control algorithm. Besides, the
proposed PLL controller ensures the grid connection of inverter without complex
control methods or complex algorithm requirement.

Keywords

Asymmetrical inverter, PI controller, PLL controller, Solar energy, Total harmonic distortion

References

• Çolak I, Kabalcı E, Bayındır R. “Review of multilevel voltage source inverter topologies and control schemes”. Energy Conversion and Management, 52, 1114-1128, 2011.
• Krishna KV, Suryawanshi HM, Shitole AB, Ajmal T. "Comparison between 2-level and 3-level grid connected inverters implemented using SRF PLL technique". International Conference on Energy, Power and Environment: Towards Sustainable Growth (ICEPE), Shillong, India, 12-13 June 2015.
• Li X, Balog RS. "PLL-less robust active and reactive power controller for single phase grid-connected inverter with LCL filter". IEEE Applied Power Electronics Conference and Exposition (APEC), Charlotte, NC, 15-19 March, 2015.
• Çolak I, Kabalcı E, Keven G. “A review on asymmetric multi-level ınverters”. EMO Bilimsel Dergi, 2(3), 137-143, 2012.
• Babaei E, Moeinian MS. “Asymmetric cascaded multilevel inverter with charge balance control of a low resolution symmetric subsystem”. Energy Conversion and Management, 51(11), 2272-2278, 2010.
• Kai D, Yunping Z, Lei L, Zhichao W, Hongyuan J, Xudong Z. "Novel hybrid cascade asymmetric inverter based on 5-level asymmetric inverter". 36th Power Electronics Specialists Conference, Recife, Brazil, 16 June 2005.
• Miranda H, Espinosa-Pe-rez G, Cárdenas V. “Passivity-based control of an asymmetric nine-level inverter for harmonic current mitigation”. Power Electronics, 5(2), 237-247, 2012.
• Colak I, Bayindir R, Kabalci E. “Design and analysis of a 7-level cascaded multilevel inverter with dual SDCSs”. International Symposium on Power Electrical Drives Automation and Motion, Pisa, Italy, 14-16 June 2010.
• Ludois DC, Reed JK, Venkataramanan G. “Hierarchical control of bridge-of-bridge multilevel power converters”. IEEE Transactions on Industrial Electronics, 57(8), 2679-2690, 2010.
• Li W. “A new approachto the harmonic analysis of SPWM waves”. IEEE International Conference on Mechatronics and Automation, Luoyang, Henan, China, 25-28 June 2006.
• Sabarad J, Kulkarni GH. “Comparative analysis of SVPWM and SPWM techniques for multilevel inverter”. International Conference on Power and Advanced Control Engineering, Bangalore, India, 12-14 August 2015.
• Colak I, Kabalci E, Bayindir R. “Review of multilevel voltage source inverter topologies and control schemes”. Energy Conversion and Management, 52(2), 1114-1128, 2011.
• Zambra DAB, Rech C, Pinheiro JR. “Comparison of Neutral-Point-Clamped, Symmetrical, and Hybrid Asymmetrical Multilevel Inverters”. IEEE Transactions on Industrial Electronics, 57(7), 2297-2306, 2010.
• Kabalci E, Kabalci Y, Canbaz R. and Gokkus G. “Single phase multilevel string inverter for solar applications”. 4th International Conference on Renewable Energy Research and Applications, Palermo, Italy, 22-25 November 2015.
• Babaei E, Hosseini SH. “New cascaded multilevel inverter topology with minimum number of switches”. Energy Conversion and Management, 50(11), 2761-2767, 2009.
• Rodriguez J, Bernet S, Wu B, Pontt JO, Kouro S. “Multilevel voltage-source-converter topologies for industrial medium-voltage drives”. IEEE Transactions on Industrial Electronics, 54(6), 2930-2945, 2007.
• Babaei E, Hosseini SH, Gharehpetian GB, Tarafdar Haque M, Sabahi M. “Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology”. Electric Power Systems Research, 77(8), 1073-1085, 2007.
• Corzine KA, Wielebski MW, Peng FJ, Wang, “Control of cascaded multi-level inverters”. IEEE International Electric Machines and Drives Conference, Madison, WI, USA, 1-4 June 2003.
• Barreto LHSC, Praca PP, Cruz CMT, Bascope RT. “PID digital control using microcontroller and FPGA applied to a single-phase three-level inverter”. 22nd APEC Applied Power Electronics Conference, Anaheim, CA, USA, 25 February-1 March 2007.
• Datta A, Ho MT, Bhattacharyya SP. Structure and Synthesis of PID Controllers. London, Britain, Springer Science & Business Media, 2000.
• Sezen S, Özdemir E. “Modeling, simulation and control of three phase three level multilevel ınverter for grid connected PV system”. SOLAR TR2 Solar Electricity Conference and Exhibition, Antalya, Turkey,7-9 November 2012.
• Ehara T. “Overcoming PV Grid Issues in The Urban Areas”. IEA, Report IEA-PVPS T10-06, Japan, 2009.