Research Article
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Year 2020, Volume: 24 Issue: 5, 1121 - 1134, 01.10.2020
https://doi.org/10.16984/saufenbilder.726396

Abstract

References

  • Calhoun BH, Daly DC, Verma N, Finchelstein DF, Wentzloff DD, Wang A, Cho SH, Chandrakasan AP. Design considerations for ultra-low energy wireless microsensor nodes. IEEE Transactions on Computers. 2005; 54(6):727-40.
  • Shikata A, Sekimoto R, Kuroda T, Ishikuro H. A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR ADC with tri-level comparator in 40 nm CMOS. IEEE Journal of Solid-State Circuits. 2012; 47(4):1022-30.
  • Ramadass YK, Chandrakasan AP. Minimum energy tracking loop with embedded DC–DC converter enabling ultra-low-voltage operation down to 250 mV in 65 nm CMOS. IEEE Journal of Solid-state circuits. 2008;43(1):256-65.
  • Perumana BG, Mukhopadhyay R, Chakraborty S, Lee CH, Laskar J. A low-power fully monolithic subthreshold CMOS receiver with integrated LO generation for 2.4 GHz wireless PAN applications. IEEE Journal of Solid-State Circuits. 2008;43(10):2229-38.
  • Cabrera-Bernal E, Pennisi S, Grasso AD, Torralba A, Carvajal RG. 0.7-V three-stage class-ABCMOS operational transconductance amplifier. IEEE Transactions on Circuits and Systems I: Regular Papers. 2016;63(11):1807-15.
  • Grasso AD, Pennisi S, Scotti G, Trifiletti A. 0.9-V Class-AB Miller OTA in 0.35um CMOS With Threshold-Lowered Non-Tailed Differential Pair. IEEE Transactions on Circuits and Systems I: Regular Papers. 2017;64(7):1740-7.
  • Ballo A, Grasso AD, Pennisi S. CMOS Differential Stage with Improved DC Gain, CMRR and PSRR Performance. 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2019 Nov 27:154-157.
  • Afacan E. Inversion coefficient optimization based Analog/RF circuit design automation. Microelectronics Journal. 2019;83:86-93.
  • Enz C, Chalkiadaki MA, Mangla A. Low-power analog/RF circuit design based on the inversion coefficient. In ESSCIRC Conference 41st European Solid-State Circuits Conference (ESSCIRC) 2015 Sep 14: 202-208.
  • Yadav C, Prasad S. Low voltage low power sub-threshold operational amplifier in 180nm cmos. In2017 Third International Conference on Sensing, Signal Processing and Security (ICSSS) 2017 May 4: 35-38.
  • Ragheb AN, Kim H. Ultra-low power OTA based on bias recycling and subthreshold operation with phase margin enhancement. Microelectronics Journal. 2017;60:94-101.
  • Eldeeb MA, Ghallab YH, Ismail Y, Elghitani H. Low-voltage subthreshold CMOS current mode circuits: Design and applications. AEU-International Journal of Electronics and Communications. 2017;82:251-64.
  • Kumar AJ, Krishna KL, Viswateja KA, Gopi K, Rao SM, Mamatha B. A High Gain Low Power Operational Amplifier using Class AB Output Stage. In2019 3rd International Conference on Computing Methodologies and Communication (ICCMC) 2019 Mar 27:pp. 409-413.
  • Póvoa R, Arya R, Canelas A, Passos F, Martins R, Lourenço N, Horta N. Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications. Microelectronics Journal. 2020;95:104675.
  • Choe SJ, Lee JS, Park SS, Yu SD. Ultra-Low-Power Class-AB Bulk-Driven OTA with Enhanced Transconductance. IEICE Transactions on Electronics. 2019;102(5):420-3.
  • Kulej T. 0.5-V bulk-driven CMOS operational amplifier. IET Circuits, Devices & Systems. 2013;7(6):352-60.
  • Zuo L, Islam SK. Low-voltage bulk-driven operational amplifier with improved transconductance. IEEE Transactions on Circuits and Systems I: Regular Papers. 2013;60(8):2084-91.
  • Chaudhry SM, Minhas UM, Abbas F. A High Gain, Bulk Driven Operational Transconductance Amplifier (OTA) for Wireless Body Area Networks. National Academy Science Letters. 2018;41(1):41-5.
  • Akbari M, Hashemipour O. A 0.6-V, 0.4-µW bulk-driven operational amplifier with rail-to-rail input/output swing. Analog Integrated Circuits and Signal Processing. 2016;86(2):341-51.
  • Kumngern M, Khateb F, Kulej T. 0.5 V bulk-driven CMOS fully differential current feedback operational amplifier. IET Circuits, Devices & Systems. 2018;13(3):314-20.
  • Sharan T, Bhadauria V. Fully differential, bulk-driven, class AB, sub-threshold OTA with enhanced slew rates and gain. Journal of Circuits, Systems and Computers. 2017;26(01):1750001.
  • Kumngern M, Khateb F, Kulej T. 0.5 V bulk-driven CMOS fully differential current feedback operational amplifier. IET Circuits, Devices & Systems. 2018;13(3):314-20.
  • Veldandi H, Shaik RA. Low-voltage PVT-insensitive bulk-driven OTA with enhanced DC gain in 65-nm CMOS process. AEU-International Journal of Electronics and Communications. 2018;90:88-96.
  • Abdelfattah O, Roberts GW, Shih I, Shih YC. An ultra-low-voltage CMOS process-insensitive self-biased OTA with rail-to-rail input range. IEEE Transactions on Circuits and Systems I: Regular Papers. 2015;62(10):2380-90.
  • Kulej T, Khateb F. Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS. International Journal of Circuit Theory and Applications. 2018 Jun;46(6):1129-43.
  • Wen B, Zhang Q, Zhao X. A two-stage CMOS OTA with enhanced transconductance and DC- gain. Analog Integrated Circuits and Signal Processing. 2019 Feb 15;98(2):257-64.
  • Cellucci D, Centurelli F, Di Stefano V, Monsurrò P, Pennisi S, et al. A. 0.6‐V CMOS cascode OTA with complementary gate‐driven gain‐boosting and forward body bias. International Journal of Circuit Theory and Applications. 2020;48:15–27.

Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology

Year 2020, Volume: 24 Issue: 5, 1121 - 1134, 01.10.2020
https://doi.org/10.16984/saufenbilder.726396

Abstract

The requirement of low-power analog circuits has been raised in recent years due to the strict limitation of power consumption in modern applications. Therefore, the trend in analog circuit design has been changed such that they are able to meet the required specifications with lower power dissipation. Design of low power operational transconductance amplifiers, which are the main building blocks in many analog applications, has been more pronounced to keep the power dissipation below certain levels. In this concern, this study presents a low power, high-performing bulk-driven 3 stages CMOS OTA in a 130 nm standard CMOS technology. The proposed circuit leverages the bulk-driven architecture at the input stage; thus it can operate under sub 1-V. The design process of the proposed OTA is explained in detail and the results are validated via post-layout simulations. The proposed OTA is powered by ±0.45 V symmetric voltage sources, where the power consumption is around 27 μW. The area overhead is only 0.0017μm2. The open-loop gain, unity gain frequency, and the phase margin are 73.24 dB, 5.167MHz, and 78o, respectively. To demonstrate the performance of the proposed circuit, a comparison is made with other circuits published in the last five years considering the well-known figures of merit (FOMs). Comparison results indicate that the proposed solution outperforms the other circuits for small-signal operation while it is the runner-up for large-signal operation.

References

  • Calhoun BH, Daly DC, Verma N, Finchelstein DF, Wentzloff DD, Wang A, Cho SH, Chandrakasan AP. Design considerations for ultra-low energy wireless microsensor nodes. IEEE Transactions on Computers. 2005; 54(6):727-40.
  • Shikata A, Sekimoto R, Kuroda T, Ishikuro H. A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR ADC with tri-level comparator in 40 nm CMOS. IEEE Journal of Solid-State Circuits. 2012; 47(4):1022-30.
  • Ramadass YK, Chandrakasan AP. Minimum energy tracking loop with embedded DC–DC converter enabling ultra-low-voltage operation down to 250 mV in 65 nm CMOS. IEEE Journal of Solid-state circuits. 2008;43(1):256-65.
  • Perumana BG, Mukhopadhyay R, Chakraborty S, Lee CH, Laskar J. A low-power fully monolithic subthreshold CMOS receiver with integrated LO generation for 2.4 GHz wireless PAN applications. IEEE Journal of Solid-State Circuits. 2008;43(10):2229-38.
  • Cabrera-Bernal E, Pennisi S, Grasso AD, Torralba A, Carvajal RG. 0.7-V three-stage class-ABCMOS operational transconductance amplifier. IEEE Transactions on Circuits and Systems I: Regular Papers. 2016;63(11):1807-15.
  • Grasso AD, Pennisi S, Scotti G, Trifiletti A. 0.9-V Class-AB Miller OTA in 0.35um CMOS With Threshold-Lowered Non-Tailed Differential Pair. IEEE Transactions on Circuits and Systems I: Regular Papers. 2017;64(7):1740-7.
  • Ballo A, Grasso AD, Pennisi S. CMOS Differential Stage with Improved DC Gain, CMRR and PSRR Performance. 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2019 Nov 27:154-157.
  • Afacan E. Inversion coefficient optimization based Analog/RF circuit design automation. Microelectronics Journal. 2019;83:86-93.
  • Enz C, Chalkiadaki MA, Mangla A. Low-power analog/RF circuit design based on the inversion coefficient. In ESSCIRC Conference 41st European Solid-State Circuits Conference (ESSCIRC) 2015 Sep 14: 202-208.
  • Yadav C, Prasad S. Low voltage low power sub-threshold operational amplifier in 180nm cmos. In2017 Third International Conference on Sensing, Signal Processing and Security (ICSSS) 2017 May 4: 35-38.
  • Ragheb AN, Kim H. Ultra-low power OTA based on bias recycling and subthreshold operation with phase margin enhancement. Microelectronics Journal. 2017;60:94-101.
  • Eldeeb MA, Ghallab YH, Ismail Y, Elghitani H. Low-voltage subthreshold CMOS current mode circuits: Design and applications. AEU-International Journal of Electronics and Communications. 2017;82:251-64.
  • Kumar AJ, Krishna KL, Viswateja KA, Gopi K, Rao SM, Mamatha B. A High Gain Low Power Operational Amplifier using Class AB Output Stage. In2019 3rd International Conference on Computing Methodologies and Communication (ICCMC) 2019 Mar 27:pp. 409-413.
  • Póvoa R, Arya R, Canelas A, Passos F, Martins R, Lourenço N, Horta N. Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications. Microelectronics Journal. 2020;95:104675.
  • Choe SJ, Lee JS, Park SS, Yu SD. Ultra-Low-Power Class-AB Bulk-Driven OTA with Enhanced Transconductance. IEICE Transactions on Electronics. 2019;102(5):420-3.
  • Kulej T. 0.5-V bulk-driven CMOS operational amplifier. IET Circuits, Devices & Systems. 2013;7(6):352-60.
  • Zuo L, Islam SK. Low-voltage bulk-driven operational amplifier with improved transconductance. IEEE Transactions on Circuits and Systems I: Regular Papers. 2013;60(8):2084-91.
  • Chaudhry SM, Minhas UM, Abbas F. A High Gain, Bulk Driven Operational Transconductance Amplifier (OTA) for Wireless Body Area Networks. National Academy Science Letters. 2018;41(1):41-5.
  • Akbari M, Hashemipour O. A 0.6-V, 0.4-µW bulk-driven operational amplifier with rail-to-rail input/output swing. Analog Integrated Circuits and Signal Processing. 2016;86(2):341-51.
  • Kumngern M, Khateb F, Kulej T. 0.5 V bulk-driven CMOS fully differential current feedback operational amplifier. IET Circuits, Devices & Systems. 2018;13(3):314-20.
  • Sharan T, Bhadauria V. Fully differential, bulk-driven, class AB, sub-threshold OTA with enhanced slew rates and gain. Journal of Circuits, Systems and Computers. 2017;26(01):1750001.
  • Kumngern M, Khateb F, Kulej T. 0.5 V bulk-driven CMOS fully differential current feedback operational amplifier. IET Circuits, Devices & Systems. 2018;13(3):314-20.
  • Veldandi H, Shaik RA. Low-voltage PVT-insensitive bulk-driven OTA with enhanced DC gain in 65-nm CMOS process. AEU-International Journal of Electronics and Communications. 2018;90:88-96.
  • Abdelfattah O, Roberts GW, Shih I, Shih YC. An ultra-low-voltage CMOS process-insensitive self-biased OTA with rail-to-rail input range. IEEE Transactions on Circuits and Systems I: Regular Papers. 2015;62(10):2380-90.
  • Kulej T, Khateb F. Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS. International Journal of Circuit Theory and Applications. 2018 Jun;46(6):1129-43.
  • Wen B, Zhang Q, Zhao X. A two-stage CMOS OTA with enhanced transconductance and DC- gain. Analog Integrated Circuits and Signal Processing. 2019 Feb 15;98(2):257-64.
  • Cellucci D, Centurelli F, Di Stefano V, Monsurrò P, Pennisi S, et al. A. 0.6‐V CMOS cascode OTA with complementary gate‐driven gain‐boosting and forward body bias. International Journal of Circuit Theory and Applications. 2020;48:15–27.
There are 27 citations in total.

Details

Primary Language English
Subjects Electrical Engineering
Journal Section Research Articles
Authors

Engin Afacan 0000-0002-1581-3894

Publication Date October 1, 2020
Submission Date April 24, 2020
Acceptance Date August 24, 2020
Published in Issue Year 2020 Volume: 24 Issue: 5

Cite

APA Afacan, E. (2020). Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology. Sakarya University Journal of Science, 24(5), 1121-1134. https://doi.org/10.16984/saufenbilder.726396
AMA Afacan E. Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology. SAUJS. October 2020;24(5):1121-1134. doi:10.16984/saufenbilder.726396
Chicago Afacan, Engin. “Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology”. Sakarya University Journal of Science 24, no. 5 (October 2020): 1121-34. https://doi.org/10.16984/saufenbilder.726396.
EndNote Afacan E (October 1, 2020) Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology. Sakarya University Journal of Science 24 5 1121–1134.
IEEE E. Afacan, “Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology”, SAUJS, vol. 24, no. 5, pp. 1121–1134, 2020, doi: 10.16984/saufenbilder.726396.
ISNAD Afacan, Engin. “Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology”. Sakarya University Journal of Science 24/5 (October 2020), 1121-1134. https://doi.org/10.16984/saufenbilder.726396.
JAMA Afacan E. Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology. SAUJS. 2020;24:1121–1134.
MLA Afacan, Engin. “Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology”. Sakarya University Journal of Science, vol. 24, no. 5, 2020, pp. 1121-34, doi:10.16984/saufenbilder.726396.
Vancouver Afacan E. Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology. SAUJS. 2020;24(5):1121-34.