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A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM

Yıl 2023, Cilt: 5 Sayı: 1, 47 - 56, 30.04.2023
https://doi.org/10.46387/bjesr.1233679

Öz

his work gives a comparison between two approaches used for improving search operation speed by using FPGA-based Binary Content Addressable Memory (BiCAM), which is a parallel type of computer memory that quickly searches for and retrieves specific data stored within the memory by assigning a unique address to each piece of data. This hardware-based technique is more efficient than traditional software-based techniques such as Linear, Binary, and hash-based. The FPGA-based BiCAM is implemented using two different approaches: using Flip-flops and Block Random Access Memory as the memory element. The performance of these implementations is evaluated through Time complexity analysis, resource utilization, and search speed. The results indicate that the Flip-flops approach is worse in terms of search speed and resource utilization compared to the other approach. With the current increasing demand for faster and more efficient search operations, this approach can play an important role in optimizing search operations.

Kaynakça

  • R.Schlesinger, “Developing Real World Software”, Jones & Bartlett Publishers, 2009.
  • H. Öztekin, F.Temurtas, and A.Gulbag, “BZK.SAU. FPGA10.1: A modular approach to FPGA-based microcomputer architecture design for educational purposes”, Computer Applications in Engineering Education, vol.22, no.2, pp.272–282, 2014.
  • R. Karam, R. Puri, S. Ghosh and S. Bhunia, "Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories," in Proceedings of the IEEE, vol. 103, no. 8, pp. 1311-1330, Aug. 2015,
  • H. Öztekin, “BiCAM-based automated scoring system for digital logic circuit diagrams”. Open Chemistry, Vol.20, No.1, pp. 1548-1556. Dec.2022
  • S. Hirasawa, H. Yamaki and M. Koibuchi, "Packet Forwarding Cache of Commodity Switches for Parallel Computers," 2021 IEEE International Conference on Cluster Computing (CLUSTER), pp. 366-376, Sep.2021,
  • D. Jothi, and R. Sivakumar, “Design and Analysis of Power Efficient Binary Content Addressable Memory (PEBCAM) Core Cells”, Circuits, Systems, and Signal Processing, vol.37, no.6, pp.1422–1451, 2018.
  • M. V. Zackriya , and H. M. Kittur, “ Precharge-Free Low-Power Content-Addressable Memory”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, no.8, pp.2614-2621, 2016.
  • M. Irfan, A.I. Sanka, Z.Ullah, and R.C.C. Cheung, “Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey”, Future Generation Computer Systems, vol.128, pp.451-465, 2021.
  • Z. Ullah, K.Ilgon, and S. Baeg, “ Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.59, pp.2969-2979, 2012.
  • A. Ahmed, K. Park, and S. Baeg, “Resource-Efficient SRAM-Based Ternary Content Addressable Memory ”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.25, pp.1583-1587, 2017.
  • J.G. Nash, “Distributed-Memory-Based FFT Archite -cture and FPGA Implementations”, Electronics, vol.7, no.7, pp.116–145, 2018.
  • Z. Ullah, “LH-CAM: Logic-Based Higher Performan -ce Binary CAM Architecture on FPGA”, IEEE Embedded Systems Letters, vol.9, no.2, pp. 29–32, 2017.
  • Z. Ullah, K. Ilgon, and S.Baeg, “Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.59, pp.2969-2979, 2012.
  • W. Jiang, “Scalable Ternary Content Addressable Memory implementation using FPGAs”, 9th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, pp.71-82. Oct. 2013.
  • Z. Qian, and M. Margala, “Low power RAM-based hierarchical CAM on FPGA”, 2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig14), pp.1-4, Dec. 2014.
  • Z. Ullah, M. K. Jaiswal, and R. C. Cheung, “Z-TCAM: an SRAM based architecture for TCAM”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, no.2, pp.402–406, 2015.
  • I. Ullah, Z. Ullah, and J. Lee, “Efficient TCAM Design Based on Multi Pumping-Enabled Multi ported SRAM on FPGA”, IEEE Access, vol.6, pp.19940-19947, 2018.
  • M. Irfan, Z. Ullah, and R. C. Cheung, “Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs”, Electronics, vol.8, no.5, pp.584-596, 2019.
  • P. Reviriego, A. Ullah, and S. Pontarelli, “PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.27, no.8, pp.1952-1956, 2019.
  • M. Irfan, Z. Ullah, and R. C. Cheung, “ D-TCAM: A High-Performance Distributed RAM Based TCAM Architecture on FPGAs”, IEEE Access, vol.7, pp.96060-96069, 2019.
  • I. Ullah, Z. Ullah, U. Afzaal, and J. Lee, “DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.27, no.6, pp.1298-1307, 2019.
  • H. Mahmood, Z. Ullah, O.M. Mujahid, I. Ullah, and A. Hafeez, “Beyond the Limits of Typical Strategies: Resources Efficient FPGA-Based TCAM”, IEEE Embedded Systems Letters, vol.11, no.3, pp.89-92, 2018.
  • [23] M. Irfan, and Z. Ullah, “G-AETCAM: Gate-Based Area-Efficient Ternary Content-Addressable Memor -y on FPGA”, IEEE Access, vol.5, pp.20785-20790 , 2017.
  • M. Irfan, H. E. Yantır, Z. Ullah and R. C. C. Cheung, "Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs," in IEEE Embedded Systems Letters, vol. 14, no. 2, pp. 63-66, 2022.
  • H. Öztekin, F. Temurtas, and A. Gulbag, “BZK. SAU. FPGA10.0: Microprocessor architecture design on reconfigurable hardware as an educational tool”, 2011 IEEE Symposium on Computers & Informatics, pp. 385-389, Mar. 2010.
  • H. Öztekin, H. Kişioğlu, A.Gülbağ, F.Temurtas, “The design and implementation of a 16 bit floating point arithmetic unit using BZK.SAU.FPGA microcomputer assembly language”. Computer Applications in Engineering Education. vol.20, no.6, pp.1834–1856, 2022.
  • H. Öztekin, A. Gülbağ, and F. Temurtaş, “ Assembler Design for BZK.SAU. FPGA Micro Computer Architecture”, Electronic Letters on Science and Engineering, vol.13, no.1, pp.1-9, 2017.
  • H. Öztekin, “ Embedded Operating System Design on Configurable Modular Hardware for Educational Purposes”, Ph.D. Thesis, Sakarya University. Institute of Science and Technology, Sakarya, 2012.
  • F. Temurtas, and A. Gulbag, “Educational Microcomputer Architecture and Embedded Operating System Design on Remote Accessible Configurable Hardware”. Proj. No. 110E069 , TÜBI TAK-EEEAG, 2012.
  • A. Boutros, and V. Betz, “FPGA Architecture: Principles and Progression”, IEEE Circuits and Systems Magazine, vol.21, no.2, pp.4-29, 2021.
  • S. Trimberger, “FPGA Technology: Past, Present, and Future”, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference, pp.12-15, Sept. 1995.
  • G. Kasivinayagam, R. Skanda, A.G. Burli, S. Jadon, and R. Sidhu, “Hardware Description Language Enhancements for High-Level Synthesis of Hardware Accelerators”, Advances in Computing and Data Sciences, vol.1613, pp.1-12, 2022.
  • S. Gandhare, and B. Karthikeyan, “Survey on FPGA Architecture and Recent Applications”, 2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN), pp. 1-4, Mar. 2019.
  • Xilinx, “Binary CAM Search LogiCORE IP Product Guide (PG317) ”, 2022, Retrieved from https://docs. xilinx.com/r/en-US/pg317-bcam/Introduction
  • Xilinx, “Ternary CAM Search LogiCORE IP Product Guide (PG318) ”, 2021, Retrieved from https://docs. xilinx.com/r/2.2-English/pg318-tcam/Introduction
  • B. MacCleery, Z. Kassas, “New Mechatronics Development Techniques for FPGA-Based Control and Simulation of Electromechanical Systems.” IFAC Proceedings, Vol. 41, no.2, 4434-4439,2008.
  • G. Dhanabalan, V. Karutharaja and M. Sakthimohan, "Realization of Resource Efficient Block RAM Based Eight Bit Adder in FPGA," 2019 IEEE International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS), pp. 1-5, April 2019.
  • M. M. Mano, “Computer System Architecture”, Prentice Hall,1993.
  • M. Sipser, “Introduction to the Theory of Computation”, Cengage Learning , 2012 .

A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM

Yıl 2023, Cilt: 5 Sayı: 1, 47 - 56, 30.04.2023
https://doi.org/10.46387/bjesr.1233679

Öz

This work gives a comparison between two approaches used for improving search operation speed by using FPGA-based Binary Content Addressable Memory (BiCAM), which is a parallel type of computer memory that quickly searches for and retrieves specific data stored within the memory by assigning a unique address to each piece of data. This hardware-based technique is more efficient than traditional software-based techniques such as Linear, Binary, and hash-based. The FPGA-based BiCAM is implemented using two different approaches: using Flip-flops and Block Random Access Memory as the memory element. The performance of these implementations is evaluated through Time complexity analysis, resource utilization, and search speed. The results indicate that the Flip-flops approach is worse in terms of search speed and resource utilization compared to the other approach. With the current increasing demand for faster and more efficient search operations, this approach can play an important role in optimizing search operations.

Kaynakça

  • R.Schlesinger, “Developing Real World Software”, Jones & Bartlett Publishers, 2009.
  • H. Öztekin, F.Temurtas, and A.Gulbag, “BZK.SAU. FPGA10.1: A modular approach to FPGA-based microcomputer architecture design for educational purposes”, Computer Applications in Engineering Education, vol.22, no.2, pp.272–282, 2014.
  • R. Karam, R. Puri, S. Ghosh and S. Bhunia, "Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories," in Proceedings of the IEEE, vol. 103, no. 8, pp. 1311-1330, Aug. 2015,
  • H. Öztekin, “BiCAM-based automated scoring system for digital logic circuit diagrams”. Open Chemistry, Vol.20, No.1, pp. 1548-1556. Dec.2022
  • S. Hirasawa, H. Yamaki and M. Koibuchi, "Packet Forwarding Cache of Commodity Switches for Parallel Computers," 2021 IEEE International Conference on Cluster Computing (CLUSTER), pp. 366-376, Sep.2021,
  • D. Jothi, and R. Sivakumar, “Design and Analysis of Power Efficient Binary Content Addressable Memory (PEBCAM) Core Cells”, Circuits, Systems, and Signal Processing, vol.37, no.6, pp.1422–1451, 2018.
  • M. V. Zackriya , and H. M. Kittur, “ Precharge-Free Low-Power Content-Addressable Memory”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, no.8, pp.2614-2621, 2016.
  • M. Irfan, A.I. Sanka, Z.Ullah, and R.C.C. Cheung, “Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey”, Future Generation Computer Systems, vol.128, pp.451-465, 2021.
  • Z. Ullah, K.Ilgon, and S. Baeg, “ Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.59, pp.2969-2979, 2012.
  • A. Ahmed, K. Park, and S. Baeg, “Resource-Efficient SRAM-Based Ternary Content Addressable Memory ”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.25, pp.1583-1587, 2017.
  • J.G. Nash, “Distributed-Memory-Based FFT Archite -cture and FPGA Implementations”, Electronics, vol.7, no.7, pp.116–145, 2018.
  • Z. Ullah, “LH-CAM: Logic-Based Higher Performan -ce Binary CAM Architecture on FPGA”, IEEE Embedded Systems Letters, vol.9, no.2, pp. 29–32, 2017.
  • Z. Ullah, K. Ilgon, and S.Baeg, “Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.59, pp.2969-2979, 2012.
  • W. Jiang, “Scalable Ternary Content Addressable Memory implementation using FPGAs”, 9th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, pp.71-82. Oct. 2013.
  • Z. Qian, and M. Margala, “Low power RAM-based hierarchical CAM on FPGA”, 2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig14), pp.1-4, Dec. 2014.
  • Z. Ullah, M. K. Jaiswal, and R. C. Cheung, “Z-TCAM: an SRAM based architecture for TCAM”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, no.2, pp.402–406, 2015.
  • I. Ullah, Z. Ullah, and J. Lee, “Efficient TCAM Design Based on Multi Pumping-Enabled Multi ported SRAM on FPGA”, IEEE Access, vol.6, pp.19940-19947, 2018.
  • M. Irfan, Z. Ullah, and R. C. Cheung, “Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs”, Electronics, vol.8, no.5, pp.584-596, 2019.
  • P. Reviriego, A. Ullah, and S. Pontarelli, “PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.27, no.8, pp.1952-1956, 2019.
  • M. Irfan, Z. Ullah, and R. C. Cheung, “ D-TCAM: A High-Performance Distributed RAM Based TCAM Architecture on FPGAs”, IEEE Access, vol.7, pp.96060-96069, 2019.
  • I. Ullah, Z. Ullah, U. Afzaal, and J. Lee, “DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.27, no.6, pp.1298-1307, 2019.
  • H. Mahmood, Z. Ullah, O.M. Mujahid, I. Ullah, and A. Hafeez, “Beyond the Limits of Typical Strategies: Resources Efficient FPGA-Based TCAM”, IEEE Embedded Systems Letters, vol.11, no.3, pp.89-92, 2018.
  • [23] M. Irfan, and Z. Ullah, “G-AETCAM: Gate-Based Area-Efficient Ternary Content-Addressable Memor -y on FPGA”, IEEE Access, vol.5, pp.20785-20790 , 2017.
  • M. Irfan, H. E. Yantır, Z. Ullah and R. C. C. Cheung, "Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs," in IEEE Embedded Systems Letters, vol. 14, no. 2, pp. 63-66, 2022.
  • H. Öztekin, F. Temurtas, and A. Gulbag, “BZK. SAU. FPGA10.0: Microprocessor architecture design on reconfigurable hardware as an educational tool”, 2011 IEEE Symposium on Computers & Informatics, pp. 385-389, Mar. 2010.
  • H. Öztekin, H. Kişioğlu, A.Gülbağ, F.Temurtas, “The design and implementation of a 16 bit floating point arithmetic unit using BZK.SAU.FPGA microcomputer assembly language”. Computer Applications in Engineering Education. vol.20, no.6, pp.1834–1856, 2022.
  • H. Öztekin, A. Gülbağ, and F. Temurtaş, “ Assembler Design for BZK.SAU. FPGA Micro Computer Architecture”, Electronic Letters on Science and Engineering, vol.13, no.1, pp.1-9, 2017.
  • H. Öztekin, “ Embedded Operating System Design on Configurable Modular Hardware for Educational Purposes”, Ph.D. Thesis, Sakarya University. Institute of Science and Technology, Sakarya, 2012.
  • F. Temurtas, and A. Gulbag, “Educational Microcomputer Architecture and Embedded Operating System Design on Remote Accessible Configurable Hardware”. Proj. No. 110E069 , TÜBI TAK-EEEAG, 2012.
  • A. Boutros, and V. Betz, “FPGA Architecture: Principles and Progression”, IEEE Circuits and Systems Magazine, vol.21, no.2, pp.4-29, 2021.
  • S. Trimberger, “FPGA Technology: Past, Present, and Future”, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference, pp.12-15, Sept. 1995.
  • G. Kasivinayagam, R. Skanda, A.G. Burli, S. Jadon, and R. Sidhu, “Hardware Description Language Enhancements for High-Level Synthesis of Hardware Accelerators”, Advances in Computing and Data Sciences, vol.1613, pp.1-12, 2022.
  • S. Gandhare, and B. Karthikeyan, “Survey on FPGA Architecture and Recent Applications”, 2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN), pp. 1-4, Mar. 2019.
  • Xilinx, “Binary CAM Search LogiCORE IP Product Guide (PG317) ”, 2022, Retrieved from https://docs. xilinx.com/r/en-US/pg317-bcam/Introduction
  • Xilinx, “Ternary CAM Search LogiCORE IP Product Guide (PG318) ”, 2021, Retrieved from https://docs. xilinx.com/r/2.2-English/pg318-tcam/Introduction
  • B. MacCleery, Z. Kassas, “New Mechatronics Development Techniques for FPGA-Based Control and Simulation of Electromechanical Systems.” IFAC Proceedings, Vol. 41, no.2, 4434-4439,2008.
  • G. Dhanabalan, V. Karutharaja and M. Sakthimohan, "Realization of Resource Efficient Block RAM Based Eight Bit Adder in FPGA," 2019 IEEE International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS), pp. 1-5, April 2019.
  • M. M. Mano, “Computer System Architecture”, Prentice Hall,1993.
  • M. Sipser, “Introduction to the Theory of Computation”, Cengage Learning , 2012 .
Toplam 39 adet kaynakça vardır.

Ayrıntılar

Birincil Dil İngilizce
Konular Yazılım Mimarisi
Bölüm Araştırma Makaleleri
Yazarlar

Halit Öztekin 0000-0001-8598-4763

İhsan Pehlivan 0000-0001-6107-655X

Abdelkader Lazzem 0000-0003-0136-356X

Yayımlanma Tarihi 30 Nisan 2023
Yayımlandığı Sayı Yıl 2023 Cilt: 5 Sayı: 1

Kaynak Göster

APA Öztekin, H., Pehlivan, İ., & Lazzem, A. (2023). A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM. Mühendislik Bilimleri Ve Araştırmaları Dergisi, 5(1), 47-56. https://doi.org/10.46387/bjesr.1233679
AMA Öztekin H, Pehlivan İ, Lazzem A. A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM. Müh.Bil.ve Araş.Dergisi. Nisan 2023;5(1):47-56. doi:10.46387/bjesr.1233679
Chicago Öztekin, Halit, İhsan Pehlivan, ve Abdelkader Lazzem. “A Case Study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM”. Mühendislik Bilimleri Ve Araştırmaları Dergisi 5, sy. 1 (Nisan 2023): 47-56. https://doi.org/10.46387/bjesr.1233679.
EndNote Öztekin H, Pehlivan İ, Lazzem A (01 Nisan 2023) A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM. Mühendislik Bilimleri ve Araştırmaları Dergisi 5 1 47–56.
IEEE H. Öztekin, İ. Pehlivan, ve A. Lazzem, “A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM”, Müh.Bil.ve Araş.Dergisi, c. 5, sy. 1, ss. 47–56, 2023, doi: 10.46387/bjesr.1233679.
ISNAD Öztekin, Halit vd. “A Case Study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM”. Mühendislik Bilimleri ve Araştırmaları Dergisi 5/1 (Nisan 2023), 47-56. https://doi.org/10.46387/bjesr.1233679.
JAMA Öztekin H, Pehlivan İ, Lazzem A. A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM. Müh.Bil.ve Araş.Dergisi. 2023;5:47–56.
MLA Öztekin, Halit vd. “A Case Study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM”. Mühendislik Bilimleri Ve Araştırmaları Dergisi, c. 5, sy. 1, 2023, ss. 47-56, doi:10.46387/bjesr.1233679.
Vancouver Öztekin H, Pehlivan İ, Lazzem A. A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM. Müh.Bil.ve Araş.Dergisi. 2023;5(1):47-56.