Esnek Ardışık-Çıkarımlı Kutupsal Kod Çözücünün FPGA Gerçeklemesi
Öz
Anahtar Kelimeler
Teşekkür
Kaynakça
- Arıkan, E. (2009). Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels. IEEE Transactions on Information Theory, 55 (7), 996–1009.
- 3GPP TSG RAN WG1 Meeting #87. (2016). On the hardware implementation of channel decoders for short block lengths. Reno, Nevada, USA.
- Tal, I., & Vardy, A. (2015). List Decoding of Polar Codes, IEEE Transactions on Information Theory, 61 (5), 2213-2226.
- Tal, I., & Vardy, A. (2011). List Decoding of Polar Codes. International Symposium on Information Theory Proceedings, 31 July - 05 August, St. Petersburg, Russia, 1-5.
- Leroux, C., Tal, I., Vardy, A., & Gross, W., J. (2011). Hardware architectures for successive cancellation decoding of polar codes. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 22-27 May, Prague, Czech Republic, 1665-1668.
- Pamuk, A. (2011). An FPGA implementation architecture for decoding of polar codes. 8th International Symposium on Wireless Communication Systems, 06-09 November, Aachen, Germany, 1665-1668.
- Sarkis, G., Giard, P., Vardy, A., Thibeault, C., & Gross, W., J. (2016). Fast List Decoders for Polar Codes. IEEE Journal on Selected Areas in Communications, 34 (2), 318-328.
- Dizdar, O., & Arıkan, E. (2016). A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic. IEEE Transactions on Circuits and Systems I: Regular Papers, 63 (3), 436-447.
Ayrıntılar
Birincil Dil
Türkçe
Konular
Mühendislik
Bölüm
Araştırma Makalesi
Yazarlar
Enver Çavuş
0000-0002-7203-9700
Türkiye
Yayımlanma Tarihi
31 Mayıs 2023
Gönderilme Tarihi
8 Temmuz 2022
Kabul Tarihi
19 Şubat 2023
Yayımlandığı Sayı
Yıl 2023 Cilt: 10 Sayı: 1