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CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT

Yıl 2014, Cilt: 14 Sayı: 2, 1791 - 1797, 25.03.2015

Öz

This paper proposes a CMOS current-mode multi_input analog multiplier and divider circuit based on a new method. Exponential and logarithmic functions are employed to realize the circuit which is used in neural network and fuzzy integrated systems. The major advantages of this multiplier are ability of having multi_input signals, and low Total Harmonic Distortion (THD). The circuit is designed and simulated using MATLAB software and HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35μm standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 0.9% and a THD of 0.42% in 1MHz. Moreover, the maximum power consumption of the circuit is found to be 0.89mW.

Kaynakça

  • B. Gibert, ―A precision four-quadrant multiplier with subnanosecond response,‖ IEEE J. Solid-State Circuits, vol. SC-3, no. 6, pp. 353-365, Dec. 1968.
  • C. Chen and Z. Li, ―A Low-power CMOS Analog multiplier,‖ IEEE Tran. Circuit Syst. II., Vol. 52, No. 9, pp. 100-104, 2006.
  • Mirko Gravati, Maurizio Valle, Giuseppe Ferri, Nicola Guerrini, ―A novel current-mode very low power analog CMOS four quadrant multiplier. Proceedings of ESSCIRC, France, IEEE, 2005.
  • A. Naderi, A. Khoei, Kh. Hadidi and H. Ghasemzadeh: ―A New High Speed and Low Power Four-Quadrant CMOS Analog Multiplier in Current-Mode‖, Int. Journal of Electronics and Communications (AEÜ), Elsevier, Volume 63, Issue 9, 2009, 769-775.
  • Montree Kumngern, and Kobchai Dejhan―Versatile DualMode Class-AB Four-Quadrant Analog Multiplier‖ International journal of signal processing, vol. 2 number ISSN 1304-4494, 2005.
  • Koichi Tanno, Okihiko Ishizuka, and Zheng Tang ―FourQuadrant CMOS Current-Mode Multiplier Independent of Device Parameters‖ IEEE transactions on circuits and systems-II vol. 47, NO. 2000.
  • Antonio j. Lopez-Martin, Alfonso Carlosena, ―Current-Mode Multi-plier/Divider Circuits Based on the MOS Translinear Principle―, Analog Integrated Circuits and Signal Processing, 28, 265–278, 2001.
  • A. Naderi, H. Mojarrad, H. Ghasemzadeh , A. Khoei and Kh. Hadidi: " Four-Quadrant CMOS Analog Multiplier Based on New Current Squarer Circuit with High-Speed", EUROCON 2009, IEEE , vol., no., pp.282,287, 18-23 May 2009.
  • Mehrvarz HR, Kwok CY. A novel multi-input floating-gate MOS four-quadrant analog multiplier. IEEE J Solid-State Circuits 1997;1123–31.
  • A. Naderi, A. Khoei, and Kh. Hadidi: ―High Speed, Low Power Four-Quadrant CMOS Current-Mode Multiplier‖, Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on , vol., no., pp.1308,1311, 11-14 Dec. 2007.
  • Chang C-C, Liu S-I. Weak inversion four-quadrant multiplier and two-quadrant divider. Electron Lett 1996;34:2079–80.
  • Y.Chen, Y.Huang, D.Liu “Current-mode defuzzifier circuit to realise the centroid strategy“, IEE Circuits Devices Syst., vol. 144, No. 5, 1997.
  • Cyril Prasanna Raj P, S.L. Pinjare, ―Design and Analog VLSI Implementation of Neural Network Architecture for Signal Processing‖, European Journal of Scientific Research ,Vol. 27, No. 2, pp. 199-216, 2009.
  • Hamid Reza Mehrvarz and Chee Yee Kwok, ―A Novel Multi-Input Floating-Gate MOS Four-Quadrant Analog Multiplier‖, IEEE Journal of Solid-State Circuits, Vol. 31, No. 8, 1996.
  • B. Razavi, ―Design of Analog CMOS Integrated Circuits‖, New York: McGraw-Hill, pp: 223-226, 2001.
  • A. Naderi, A. Khoei and Kh. Hadidi : ―Circuit Implementation of High-Resolution Rational-Powered Membership Functions in Standard CMOS Technology‖, Analog Integrated Circuits and Signal Processing, Springer, Vol. 65, No. 2, 217-223, 2010.
  • S. Vlassis, ―CMOS Current-Mode Pseudo-Exponential Function Circuit,‖ Electron. Lett., vol. 37, no. 8, Apr. 2001, pp. 471-472.
  • A. Naderi and S. Ozoguz, ―A New CMOS Exponential Circuit with Extended Linear Output Range‖, Circuit Theory and Design (ECCTD), 2011 20th European Conference on , vol., no., pp.893,896, 29-31 Aug. 2011.
  • K. T. Lau, S.T. Lee, V.K.S. Ong, ―Four-quadrant analog CMOS multiplier cell for VLSI signal and information processing‖, IEE Proceedings on Circuits, Devices and Systems, Vol. 145, No. 2, April, 1998, pp. 132-134.
  • Ali Naderi Saatlo was born in Urmia, Iran, in 1982. He received his B.Sc. degree in Communication Engineering from Urmia Azad University, Urmia, Iran, in 2005, and M.Sc. degree in Electrical Engineering from Urmia University in 2008. He is currently PhD student of Electrical and Electronics Engineering in Institute of Science and Technology of Istanbul Technical University, Istanbul, Turkey. Since 2011, he has been a faculty member of electrical engineering department of Urmia Azad University, Urmia, Iran. His research interests are analog and digital integrated circuit design for fuzzy applications, fuzzy sets and systems, high performance analog circuits, and digital signal processing. He is the author or coauthor of more than 20 peer-reviewed papers in international and national journals and conference proceedings.
Yıl 2014, Cilt: 14 Sayı: 2, 1791 - 1797, 25.03.2015

Öz

Kaynakça

  • B. Gibert, ―A precision four-quadrant multiplier with subnanosecond response,‖ IEEE J. Solid-State Circuits, vol. SC-3, no. 6, pp. 353-365, Dec. 1968.
  • C. Chen and Z. Li, ―A Low-power CMOS Analog multiplier,‖ IEEE Tran. Circuit Syst. II., Vol. 52, No. 9, pp. 100-104, 2006.
  • Mirko Gravati, Maurizio Valle, Giuseppe Ferri, Nicola Guerrini, ―A novel current-mode very low power analog CMOS four quadrant multiplier. Proceedings of ESSCIRC, France, IEEE, 2005.
  • A. Naderi, A. Khoei, Kh. Hadidi and H. Ghasemzadeh: ―A New High Speed and Low Power Four-Quadrant CMOS Analog Multiplier in Current-Mode‖, Int. Journal of Electronics and Communications (AEÜ), Elsevier, Volume 63, Issue 9, 2009, 769-775.
  • Montree Kumngern, and Kobchai Dejhan―Versatile DualMode Class-AB Four-Quadrant Analog Multiplier‖ International journal of signal processing, vol. 2 number ISSN 1304-4494, 2005.
  • Koichi Tanno, Okihiko Ishizuka, and Zheng Tang ―FourQuadrant CMOS Current-Mode Multiplier Independent of Device Parameters‖ IEEE transactions on circuits and systems-II vol. 47, NO. 2000.
  • Antonio j. Lopez-Martin, Alfonso Carlosena, ―Current-Mode Multi-plier/Divider Circuits Based on the MOS Translinear Principle―, Analog Integrated Circuits and Signal Processing, 28, 265–278, 2001.
  • A. Naderi, H. Mojarrad, H. Ghasemzadeh , A. Khoei and Kh. Hadidi: " Four-Quadrant CMOS Analog Multiplier Based on New Current Squarer Circuit with High-Speed", EUROCON 2009, IEEE , vol., no., pp.282,287, 18-23 May 2009.
  • Mehrvarz HR, Kwok CY. A novel multi-input floating-gate MOS four-quadrant analog multiplier. IEEE J Solid-State Circuits 1997;1123–31.
  • A. Naderi, A. Khoei, and Kh. Hadidi: ―High Speed, Low Power Four-Quadrant CMOS Current-Mode Multiplier‖, Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on , vol., no., pp.1308,1311, 11-14 Dec. 2007.
  • Chang C-C, Liu S-I. Weak inversion four-quadrant multiplier and two-quadrant divider. Electron Lett 1996;34:2079–80.
  • Y.Chen, Y.Huang, D.Liu “Current-mode defuzzifier circuit to realise the centroid strategy“, IEE Circuits Devices Syst., vol. 144, No. 5, 1997.
  • Cyril Prasanna Raj P, S.L. Pinjare, ―Design and Analog VLSI Implementation of Neural Network Architecture for Signal Processing‖, European Journal of Scientific Research ,Vol. 27, No. 2, pp. 199-216, 2009.
  • Hamid Reza Mehrvarz and Chee Yee Kwok, ―A Novel Multi-Input Floating-Gate MOS Four-Quadrant Analog Multiplier‖, IEEE Journal of Solid-State Circuits, Vol. 31, No. 8, 1996.
  • B. Razavi, ―Design of Analog CMOS Integrated Circuits‖, New York: McGraw-Hill, pp: 223-226, 2001.
  • A. Naderi, A. Khoei and Kh. Hadidi : ―Circuit Implementation of High-Resolution Rational-Powered Membership Functions in Standard CMOS Technology‖, Analog Integrated Circuits and Signal Processing, Springer, Vol. 65, No. 2, 217-223, 2010.
  • S. Vlassis, ―CMOS Current-Mode Pseudo-Exponential Function Circuit,‖ Electron. Lett., vol. 37, no. 8, Apr. 2001, pp. 471-472.
  • A. Naderi and S. Ozoguz, ―A New CMOS Exponential Circuit with Extended Linear Output Range‖, Circuit Theory and Design (ECCTD), 2011 20th European Conference on , vol., no., pp.893,896, 29-31 Aug. 2011.
  • K. T. Lau, S.T. Lee, V.K.S. Ong, ―Four-quadrant analog CMOS multiplier cell for VLSI signal and information processing‖, IEE Proceedings on Circuits, Devices and Systems, Vol. 145, No. 2, April, 1998, pp. 132-134.
  • Ali Naderi Saatlo was born in Urmia, Iran, in 1982. He received his B.Sc. degree in Communication Engineering from Urmia Azad University, Urmia, Iran, in 2005, and M.Sc. degree in Electrical Engineering from Urmia University in 2008. He is currently PhD student of Electrical and Electronics Engineering in Institute of Science and Technology of Istanbul Technical University, Istanbul, Turkey. Since 2011, he has been a faculty member of electrical engineering department of Urmia Azad University, Urmia, Iran. His research interests are analog and digital integrated circuit design for fuzzy applications, fuzzy sets and systems, high performance analog circuits, and digital signal processing. He is the author or coauthor of more than 20 peer-reviewed papers in international and national journals and conference proceedings.
Toplam 20 adet kaynakça vardır.

Ayrıntılar

Birincil Dil İngilizce
Bölüm Makaleler
Yazarlar

Ali Saatlo

Yayımlanma Tarihi 25 Mart 2015
Yayımlandığı Sayı Yıl 2014 Cilt: 14 Sayı: 2

Kaynak Göster

APA Saatlo, A. (2015). CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT. IU-Journal of Electrical & Electronics Engineering, 14(2), 1791-1797.
AMA Saatlo A. CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT. IU-Journal of Electrical & Electronics Engineering. Mart 2015;14(2):1791-1797.
Chicago Saatlo, Ali. “CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT”. IU-Journal of Electrical & Electronics Engineering 14, sy. 2 (Mart 2015): 1791-97.
EndNote Saatlo A (01 Mart 2015) CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT. IU-Journal of Electrical & Electronics Engineering 14 2 1791–1797.
IEEE A. Saatlo, “CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT”, IU-Journal of Electrical & Electronics Engineering, c. 14, sy. 2, ss. 1791–1797, 2015.
ISNAD Saatlo, Ali. “CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT”. IU-Journal of Electrical & Electronics Engineering 14/2 (Mart 2015), 1791-1797.
JAMA Saatlo A. CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT. IU-Journal of Electrical & Electronics Engineering. 2015;14:1791–1797.
MLA Saatlo, Ali. “CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT”. IU-Journal of Electrical & Electronics Engineering, c. 14, sy. 2, 2015, ss. 1791-7.
Vancouver Saatlo A. CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT. IU-Journal of Electrical & Electronics Engineering. 2015;14(2):1791-7.