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Implementation of Single-Scan Connected Component Labeling for FPGA Hardware

Cilt: 7 Sayı: 1 30 Nisan 2025
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Implementation of Single-Scan Connected Component Labeling for FPGA Hardware

Öz

Image processing is a branch of computer science that tries to extract information and identify objects from digital photographs through processing and analysis. Today, imaging systems are used in almost every aspect of our lives, particularly in medicine, the defense industry, security, automobile, and automation. As a result, the image must be processed in accordance with the intended purposes. Blob detection is a concept used in image processing to recognize and detect objects. It refers to a group of pixels that define the borders of an object in the image. Blob analysis algorithms vary. One of these techniques is the linked component labeling algorithm, which is commonly used in image processing and assigns the same label to all pixels of an object. In this study, the connected component labeling algorithm for detecting objects in the image was prepared to be implemented on the FPGA structure and tested in a simulation environment. Since processing a full image frame at once is inefficient in terms of memory resources, the image was read and processed line by line. Each pixel was labeled in a single pass through the image frame, and the area, boundaries, and centroid of each blob were determined by combining the corresponding pixels. This provides the foundation for the application of the CCL algorithm, allowing the use of PL-PS structures together. Future research will focus on constructing an efficient system that applies the blob identification procedure to the PS and PL components of the ZYNQ structure.

Anahtar Kelimeler

Blob analysis, Connected Component Labeling, FPGA

Kaynakça

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Kaynak Göster

APA
Yabanova, İ., & Ünler, T. (2025). Implementation of Single-Scan Connected Component Labeling for FPGA Hardware. Necmettin Erbakan University Journal of Science and Engineering, 7(1), 12-21. https://izlik.org/JA63JM86XA
AMA
1.Yabanova İ, Ünler T. Implementation of Single-Scan Connected Component Labeling for FPGA Hardware. NEU Fen Muh Bil Der. 2025;7(1):12-21. https://izlik.org/JA63JM86XA
Chicago
Yabanova, İsmail, ve Tarık Ünler. 2025. “Implementation of Single-Scan Connected Component Labeling for FPGA Hardware”. Necmettin Erbakan University Journal of Science and Engineering 7 (1): 12-21. https://izlik.org/JA63JM86XA.
EndNote
Yabanova İ, Ünler T (01 Nisan 2025) Implementation of Single-Scan Connected Component Labeling for FPGA Hardware. Necmettin Erbakan University Journal of Science and Engineering 7 1 12–21.
IEEE
[1]İ. Yabanova ve T. Ünler, “Implementation of Single-Scan Connected Component Labeling for FPGA Hardware”, NEU Fen Muh Bil Der, c. 7, sy 1, ss. 12–21, Nis. 2025, [çevrimiçi]. Erişim adresi: https://izlik.org/JA63JM86XA
ISNAD
Yabanova, İsmail - Ünler, Tarık. “Implementation of Single-Scan Connected Component Labeling for FPGA Hardware”. Necmettin Erbakan University Journal of Science and Engineering 7/1 (01 Nisan 2025): 12-21. https://izlik.org/JA63JM86XA.
JAMA
1.Yabanova İ, Ünler T. Implementation of Single-Scan Connected Component Labeling for FPGA Hardware. NEU Fen Muh Bil Der. 2025;7:12–21.
MLA
Yabanova, İsmail, ve Tarık Ünler. “Implementation of Single-Scan Connected Component Labeling for FPGA Hardware”. Necmettin Erbakan University Journal of Science and Engineering, c. 7, sy 1, Nisan 2025, ss. 12-21, https://izlik.org/JA63JM86XA.
Vancouver
1.İsmail Yabanova, Tarık Ünler. Implementation of Single-Scan Connected Component Labeling for FPGA Hardware. NEU Fen Muh Bil Der [Internet]. 01 Nisan 2025;7(1):12-21. Erişim adresi: https://izlik.org/JA63JM86XA