Üretilmiş memristörlerin iki farklı yöntem ile modellenmesi

Öz

İki tür Titanyum Oksit tabanlı memristif aygıt üretilmiştir. Aygıtlardan biri akım sinyali ile, diğeri ise gerilimle uyarılarak karakterize edilmiştir. Bu aygıtların modelleme çalışması iki farklı modelleme yaklaşımı kullanılarak yapılmıştır. Yaklaşımların ilkinde MATLAB’da ölçüm verisine eğri uydurma tekniği kullanılarak özgün modeller elde edilmiştir. İkincisinde ise mevcut bir model olan Quasi-Static Memdiode Model (QMM) incelenmiş ve üretilmiş aygıtlara uyarlanmıştır. Bu sayede iki farklı giriş değişkeni için modeller elde edilmiştir. Modeller SPICE ve Verilog-A dillerinde geliştirilmiştir. Bunun amacı bu memristörleri SPICE ve Cadence Spectre platformlarında simüle edebilmek ve bu sayede hibrit memristör+ CMOS devreler tasarlayabilmektir. Modellerin gerçek davranışa sadakati gerçek ölçüm verisi ve modellerin davranışları kıyaslanarak doğrulanmıştır.

Anahtar Kelimeler

• Memristör
• Aygıt Modelleme
• SPICE
• Verilog-A Eğri Uydurma

Deriving models of fabricated memristors using two approaches

Abstract

Two distinct Titanium Oxide based memristive devices were fabricated. One device was electrically characterized with a driving current, the other with a driving voltage. Two approaches were utilized for modelling these devices: firstly, novel models of I-V behavior were developed using curve fitting in MATLAB. Secondly, an existing memristor model, Quasi-Static Memdiode Model (QMM) was investigated and modified to reflect the behavior of the fabricated memristive devices. Thus, models for both current driven and voltage driven devices were extracted. SPICE and Verilog-A coding languages were used to simulate the devices in SPICE and Cadence Spectre to enable the simulation and design of hybrid memristor+ CMOS circuits on these widely used platforms. The accuracy of the models was verified by comparing simulation results to measurement results.

Keywords

• Memristor
• Device Modelling
• SPICE
• Verilog-A Curve Fitting

Kaynakça

1. [1] L. Chua, “Memristor-The missing circuit element,” IEEE Transactions on Circuit Theory, vol. 18, no. 5, pp. 507–519, Sep. 1971, doi: 10.1109/TCT.1971.1083337.
2. [2] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The missing memristor found,” Nature, vol. 453, no. 7191, Art. no. 7191, May 2008, doi: 10.1038/nature06932.
3. [3] R. S. Williams, “How We Found the Missing Memristor,” IEEE Spectrum. Accessed: Mar. 30, 2022. [Online]. Available: https://spectrum.ieee.org/how-we-found-the-missing-memristor
4. [4] Y. Ho, G. M. Huang, and P. Li, “Dynamical Properties and Design Analysis for Nonvolatile Memristor Memories,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 4, pp. 724–736, Apr. 2011, doi: 10.1109/TCSI.2010.2078710.
5. [5] M. A. Zidan, J. P. Strachan, and W. D. Lu, “The future of electronics based on memristive systems,” Nat Electron, vol. 1, no. 1, Art. no. 1, Jan. 2018, doi: 10.1038/s41928-017-0006-8.
6. [6] L. O. Chua and S. M. Kang, “Memristive devices and systems,” Proceedings of the IEEE, vol. 64, no. 2, pp. 209–223, Feb. 1976, doi: 10.1109/PROC.1976.10092.
7. [7] S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, “Nanoscale Memristor Device as Synapse in Neuromorphic Systems,” Nano Lett., vol. 10, no. 4, pp. 1297–1301, Apr. 2010, doi: 10.1021/nl904092h.
8. [8] B. Linares-Barranco, T. Serrano-Gotarredona, L. A. Camuñas-Mesa, J. A. Perez-Carrasco, C. Zamarreño-Ramos, and T. Masquelier, “On Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex,” Front. Neurosci., vol. 5, 2011, doi: 10.3389/fnins.2011.00026.

9. [9] IEEE, “International Roadmap for Devices and Systems 2021 Update: Beyond CMOS,” 2021.
10. [10] J. J. Yang, D. B. Strukov, and D. R. Stewart, “Memristive devices for computing,” Nature Nanotech, vol. 8, no. 1, Art. no. 1, Jan. 2013, doi: 10.1038/nnano.2012.240.
11. [11] J. Wyrick et al., “Atom-by-Atom Fabrication of Single and Few Dopant Quantum Devices,” Advanced Functional Materials, vol. 29, no. 52, p. 1903475, 2019, doi: 10.1002/adfm.201903475.
12. [12] İ. Orak and A. Koçyiğit, “The thickness effect of insulator layer between the semiconductor and metal contact on C-V characteristics of Al/Si3N4/p-Si device,” Pamukkale J Eng Sci, vol. 23, no. 5, pp. 536–542, 2017, doi: 10.5505/pajes.2016.23911.
13. [13] E. M. Drakakis and A. J. Payne, “A Bernoulli Cell-Based Investigation of the Non-Linear Dynamics in Log-Domain Structures,” in Research Perspectives on Dynamic Translinear and Log-Domain Circuits, W. A. Serdijn and J. Mulder, Eds., Boston, MA: Springer US, 2000, pp. 21–40. doi: 10.1007/978-1-4757-6414-7_2.
14. [14] I. Köymen and E. M. Drakakis, “Current-input current-output analog half center oscillator and central pattern generator circuits with memristors,” International Journal of Circuit Theory and Applications, vol. 46, no. 7, pp. 1294–1310, 2018, doi: 10.1002/cta.2487.
15. [15] N. Korkmaz and İ. E. Saçu, “An alternative approach for the circuit synthesis of the fractional-order FitzHugh-Nagumo neuron model,” Pamukkale J Eng Sci, vol. 28, no. 2, pp. 248–254, 2022, doi: 10.5505/pajes.2021.09382.
16. [16] Y. Pershin, S. Fontaine, and M. Di Ventra, “Memristive model of amoeba’s learning,” Nature Precedings, vol. 80, Jan. 2009, doi: 10.1038/npre.2008.2431.1.
17. [17] T. Serrano-Gotarredona, T. Masquelier, T. Prodromakis, G. Indiveri, and B. Linares-Barranco, “STDP and STDP variations with memristors for spiking neuromorphic learning systems,” Frontiers in Neuroscience, vol. 7, 2013, Accessed: Dec. 08, 2023. [Online]. Available: https://www.frontiersin.org/articles/10.3389/fnins.2013.00002
18. [18] M. Hansen, F. Zahari, H. Kohlstedt, and M. Ziegler, “Unsupervised Hebbian learning experimentally realized with analogue memristive crossbar arrays,” Sci Rep, vol. 8, no. 1, Art. no. 1, Jun. 2018, doi: 10.1038/s41598-018-27033-9.
19. [19] C. Yakopcic, T. M. Taha, G. Subramanyam, and R. E. Pino, “Generalized Memristive Device SPICE Model and its Application in Circuit Design,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 32, no. 8, pp. 1201–1214, Aug. 2013, doi: 10.1109/TCAD.2013.2252057.
20. [20] S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, “VTEAM: A General Model for Voltage-Controlled Memristors,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 8, pp. 786–790, Aug. 2015, doi: 10.1109/TCSII.2015.2433536.
21. [21] F. Merrikh Bayat, B. Hoskins, and D. B. Strukov, “Phenomenological modeling of memristive devices,” Appl. Phys. A, vol. 118, no. 3, pp. 779–786, Mar. 2015, doi: 10.1007/s00339-015-8993-7.
22. [22] F. L. Aguirre, J. Suñé, and E. Miranda, “SPICE Implementation of the Dynamic Memdiode Model for Bipolar Resistive Switching Devices,” Micromachines, vol. 13, no. 2, Art. no. 2, Feb. 2022, doi: 10.3390/mi13020330.
23. [23] M. Saludes-Tapia, M. B. Gonzalez, F. Campabadal, J. Suñé, and E. Miranda, “A simple, robust, and accurate compact model for a wide variety of complementary resistive switching devices,” Solid-State Electronics, vol. 185, p. 108083, Nov. 2021, doi: 10.1016/j.sse.2021.108083.
24. [24] J. Blasco, N. Ghenzi, J. Suãé, P. Levy, and E. Miranda, “Modeling of the Hysteretic I-V Characteristics of \rm TiO_2-Based Resistive Switches Using the Generalized Diode Equation,” IEEE Electron Device Letters, vol. 35, no. 3, pp. 390–392, Mar. 2014, doi: 10.1109/LED.2014.2297992.
25. [25] E. Miranda, “Compact Model for the Major and Minor Hysteretic I–V Loops in Nonlinear Memristive Devices,” IEEE Transactions on Nanotechnology, vol. 14, no. 5, pp. 787–789, Sep. 2015, doi: 10.1109/TNANO.2015.2455235.
26. [26] P. S. Georgiou, S. N. Yaliraki, E. M. Drakakis, and M. Barahona, “Quantitative measure of hysteresis for memristors through explicit dynamics,” Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences, Aug. 2012, doi: 10.1098/rspa.2011.0585.
27. [27] W. Zhou, S. Wen, Y. Liu, L. Liu, X. Liu, and L. Chen, “Forgetting memristor based STDP learning circuit for neural networks,” Neural Networks, vol. 158, pp. 293–304, Jan. 2023, doi: 10.1016/j.neunet.2022.11.023.
28. [28] R. Gou et al., “Actual origin and precise control of asymmetrical hysteresis in an individual CH 3 NH 3 PbI 3 micro/nanowire for optical memory and logic operation,” Nanoscale Horizons, vol. 7, no. 9, pp. 1095–1108, 2022, doi: 10.1039/D2NH00209D.