KARMAŞIK ELEKTRONİK ÜRÜNLER İÇİN TEST EKONOMİSİ

Öz

Elektronik ürünler, yakın geçmişte ortaya çıkmış ve dünyanın ekonomik düzenini tamamen değiştirecek bir şekilde inanılmaz bir hızla gelişmiş ve karmaşıklaşmıştır. Bunun doğal bir sonucu olarak, belirli kalite özelliklerine sahip olması gereken bu ürünlerin test edilmesi, hem teknik hem de ekonomik olarak zorlu problemler olarak araştırmacıların karşısına çıkmıştır. Bu çalışmada anılan ürünlere dair test süreçlerinin önemi, gelişimi, değişimi, yönetsel alanlarla zaman içinde oluşan ortak çalışma alanlarına dair bir inceleme yapılmıştır

Anahtar Kelimeler

• Test Ekonomisi
• Kalite Kontrol
• Test Stratejisi
• Test Maliyeti
• Test Ekipmanı Optimizasyonu

TEST ECONOMICS FOR COMPLEX ELECTRONIC PRODUCTS

Öz

Electronic products have displayed an incredible progress and became more and more complicated in a very fast manner that would change economic order of the world entirely. As a result, testing of these products which require certain quality characteristics has provided challenging problems for the research community both in terms of technical and economical aspects. This article focuses on presenting the importance, progress, changes and the common areas of research for the engineering and managerial sciences on the economical test problem.

Anahtar Kelimeler

• Test Economy
• Quality Control
• Test Strategy
• Test Cost
• Test Equipment Optimization

Kaynakça

1. • ABADIR, M., (1998), Economics Modeling of Multichip Modules Testing Strategies, IEEE Transactions on Components, Packaging, and Manufacturing Technology – Part B, 21, 4, 360 – 370.
2. • ADAMS, J. B., HOCHBAUM, D. S., (1997), A New and Fast Approach to Very Large Scale Integrated Sequential Circuit Test Generation, Operations Research, 45, 6, 842- 856.
3. • AGRAWAL, V. D., SETH, S. C., AGRAWAL, P., (1982), Fault Coverage Requirements in Production Testing of LSI Circuits, IEEE Journal of Solid State Circuits, 17, 1, 57 – 61.
4. • ALI, L., SIDEK, R., ARIS, I., WAGIRAN, R., ALI, M. A. M., (2004), Design of a SOC for Low Cost IC Testing, Proceedings of the IEEE ICSE2004, 374 – 378.
5. • AMBLER, A., (2001), The Cost of Test, Proceedings of the IEEE Automatic Test Conference AUTOTESCON, 515 – 523.
6. • BEDOLSE, J., RAINA, R., CROUCH, A., ABADIR, M. S., (2001), Very Low Cost Testers: Opportunities and Challenges, IEEE Design & Test of Computers, International Test Conference, 60 – 69.
7. • BIASIZZO, A., ŽUŹEK, A., NOVAK, F., (1998), Sequential Diagnosis with Asymmetrical Tests, The Computer Journal, 41, 3, 163 – 170.
8. • BOUMEN, R., DE JONG, I. S. M., VERMUNT, J. M. H., VAN DE MORTEL-FRONCZAK, J. M., ROODA, J. E., (2008), A Risk-Based Stopping Criterion for Test Sequencing, IEEE Transactıons On Systems, Man and Cybernetıcs—Part A: Systems and Humans, 38, 6, 1363 – 1373.

9. • BROWN, M., PROSCHAN, F., (1983), Imperfect Repair, Journal of Applied Probability, 20, 851 – 859.
10. • BUTTERWORTH, R., (1972), Some Reliability Fault – Testing Models, Operations Research, 20, 2, 335 – 343.
11. • CHEN, T., KIM, V.-K., TEGETHOFF, M., (1999), IC Manufacturing Test Cost Estimation at Early Stages of the Design Cycle, Microelectronics Journal, 30, 733 – 738.
12. • CHEVALIER, P. B., WEIN, L. M., (1997), Inspection for Circuit Board Assembly, Management Science, 43, 9, 1198 – 1213.
13. • DEAR, I. D., DISLIS, C., AMBLER, A. P., DICK, J., (1991), Economic Effects in Design and Test, IEEE Design and Test of Computers, 64 – 77.
14. • DICK, J. H., TRISCHLER, E., DISLIS, C., AMBLER, A. P., (1994), Sensitivity Analysis in Economic Based Test Strategy Planning, Journal of Electronic Testing: Theory and Applications (JETTA), 5, 239 – 252.
15. • DING, J., GREENBERG, B. S., MATSUO, H., (1998), Repetitive Testing Strategies When the Testing Process Is Imperfect, Management Science, 44, 10, 1367 -1378.
16. • DING, J., GREENBERG, B. S., MATSUO, H., (2010), Repetitive Testing of Multiple Products with Limited Capacity, International Journal of Quality & Reliability Management, 27, 2, 247 – 264.
17. -
18. • DISLIS, C., ALANI, A. F., JALOWIECKI, I. P., (1997), A Framework for the Management of MCM Test Strategies, Proceedings of IEEE International Conference of Multichip Modules, 272 – 277.
19. • DISLIS, C., AMBLER, A. P., DEAR, I. D., DICK, J. H., (1993), Economics in Test and Design, Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors ICCD’93, 384 – 387.
20. • DISLIS, C., DEAR, I. D., LAU, S. C., MILES, J. R., AMBLER, A. P., (1988), Hierarchical Test Strategy Planning Based on Cost Evaluation, IEE Colloquium on Computer Aided Test and Diagnosis, 7/1 – 7/8.
21. • DISLIS, C., DEAR, I. D., MILES, J. R., LAU, S. C., AMBLER, A. P., (1989), Cost Analysis of Test Method Environments, Proceedings of International Test Conference, 875 – 883.
22. • DISLIS, C., DICK, J., AMBLER, A. P., (1993), Algorithms for Cost Optimised Test Strategy Selection, Proceedings of IEEE International Test Conference, 383 – 391.
23. • DISLIS, C., DICK, J. H., DEAR, I. D., AZU, I. N., AMBLER, A. P., (1993), Economic Modeling for the Determination of Test Strategies for Complex VLSI Boards, Proceedings of International Test Conference, 210 – 217.
24. • EBADI, Z. S., IVANOV, A., (2001), Design of an Optimal Test Access Architecture Using a Genetic Algorithm, Proceedings of the 10th IEEE Asian Test Symposium, 205 – 210.
25. • EMMONS, H., RABINOWITZ, G., (2002), Inspection Allocation for Multistage Deteriorating Production Systems, IIE Transactions, 34, 1031 – 1041.
26. • EVANS, A. C., (1999), Applications of Semiconductor Test Economics, and Multisite Testing to Lower Cost of Test, Proceedings of the IEEE International Test Conference, 113 – 123.
27. • FINCH, T., (1975), LSI Test Strategies: Present and Future, Proceedings of the IEEE Solid – State Circuits Conference ISSCC.
28. • FIRSTMAN, S. I., GLUSS, B., (1960), Optimum Search Routines for Automatic Fault Location, Operations Research, 8, 4, 512 – 523.
29. • FISHER, E., FORTUNE, S., GLADSTEIN, M., GOYAL, S., LYONS, W. B., MOSHER, J., WILFONG, G., (2007a), Economic Modeling of Global Test Strategy I: Mathematical Models, Bell Labs Technical Journal, 12, 1, 161 – 173.
30. • FISHER, E., FORTUNE, S., GLADSTEIN, M., GOYAL, S., LYONS, W. B., MOSHER, J., WILFONG, G., (2007b), Economic Modeling of Global Test Strategy II: Software System and Examples, Bell Labs Technical Journal, 12, 1, 175 – 186.
31. • FLEHINGER, B. J., (1965), Product Test Planning for Repairable Systems, Technometrics, 7, 4, 485 – 494.
32. • GLUSS, B., (1959), An Optimum Policy for Detecting a Fault in a Complex System, Operations Research, 7, 4, 468 – 477.
33. • GOYAL, S., MOSHER, J. H., (2006), An Improved Test Process Model for Cost Reduction, Bell Labs Technical Journal, 11, 1, 173 – 190.
34. • HASHEMPOUR, H., MEYER, F. J., LOMBARDI, F., KARIMI, F., (2003), Hybrid Multisite Testing at Manufacturing, Proceedings of the IEEE International Test Conference, 927 – 936.
35. • HAWKINS, C. F., NAGLE, H. T., FRITZMEIER, R. R., GUTH, J. R., (1989), The VLSI Circuit Test Problem – A Tutorial, IEEE Transactions on Industrial Electronics, 36, 2, 111 – 116.
36. • KAPUR, R., CHANDRAMOULI, R., WILLIAMS, T. W., (2001), Strategies for Low – Cost Test, IEEE Design and Test of Computers, 47 – 54.
37. • KOYUNCU, O., (2007), Ekonomik Test Tasarımı ve Optimizasyonu için Kısıt Programlama Kullanılması, Yayınlanmamış Doktora Tez Çalışması, Hacettepe Üniversitesi, Ankara.
38. • MALY, W., (2001), The Design and Test Cost Problem, IEEE Design and Test of Computers, 6.
39. • MALY, W., STROJWAS, A. J., DIRECTOR, S. W., (1986), VLSI Yield Prediction and Estimation: A Unified Framework, IEEE Transactions on Computer Aided Design, 5, 1, 114 – 130.
40. • MAXWELL, P. C., AITKEN, R. C., (1993), Test Sets and Reject Rates: All Fault Coverages Are Not Created Equal, IEEE Design and Test of Computers, 42 – 51.
41. • MOORE, T. J., (1994), A Test Process Optimization and Cost Modeling Tool, Proceedings of the IEEE International Test Conference, 103 – 110.
42. • NACHLAS, J. A., LONEY, S. R., BINNEY, B. A., (1990), Diagnostic – Strategy Selection for Series Systems, IEEE Transactions on Reliability, 39, 3, 273 – 280.
43. • OPPERMANN, M., SAUER, W., WOHLRABE, W., (2001), Optimization of Inspection Strategies by Use of Quality Cost Models and SPC, 24th International Spring Seminar on Electronics Technology (IEEE ISSE 2001), 293 – 297.
44. • OPPERMANN, M., SAUER, W., WOHLRABE, W., (2003), Optimization of Quality Costs, Robotics and Computer Integrated Manufacturing, 19, 135 – 140.
45. • PATTIPATI, K. R., ALEXANDRIDIS, M. G., (1990), Application of Heuristic Search and Information Theory to Sequential Fault Analysis, IEEE Transactions on Systems, Manufacturing and Cybernetics, 20, 4, 872 – 887.
46. • POUGET, J., LARSSON, E., PENG, Z., (2003), SOC Test Time Minimization Under Multiple Constraints, Proceedings of the 12th Asian Test Symposium (ATS’03).
47. • RIVOIR, J., (2003), Lowering Cost of Test: Parallel Test or Low Cost ATE? Proceedings of the 12th IEEE Asian Test Symposium (ATS’03).
48. • RIVOIR, J., (2004), Parallel Test Reduces Cost of Test More Effectively Than Just a Cheap Tester, Proceedings of the IEEE / SEMI International Electronics Manufacturing Technology Symposium.
49. • ROBINSON, G. D. (1989), Test Program Development Using Multiple Test Strategies, Proceedings of the IEEE Automatic Testing Conference AUTOTESCON’89, 9 – 18.
50. • ROSSI, R., TARIM, S. A., HNICH, B., PRESTWICH, S., (2006), Multi-Component Testing in Telecommunications, Proceedings of the European Conference on Operational Research EURO XXI.
51. • SCHEFFLER, M., AMMANN, D., THIEL, A., HABIGER, C., TRÖSTER, G., (1998), Modeling and Optimizing the Costs of Electronic Systems, IEEE Design and Test of Computers, 20 – 26.
52. • STAPPER, C. H., ARMSTRONG, F. M., SAJI, K., (1983), Integrated Circuit Yield Statistics, Proceedings of the IEEE, 71, 4, 453 – 470.
53. • THATCHER, C. W., (1993), Design – For – Testability Economics, Proceedings of the IEEE International Test Conference.
54. • VOLKERINK, E. H., KHOCHE, A., KAMAS, L. A., RIVOIR, J., KERKHOFF, H. G., (2001), Tackling Test Trade – Offs from Design, Manufacturing to Market Using Economic Modeling, Proceedings of the IEEE International Test Conference, 1098 – 1107.
55. • VOLKERINK, E. H., KHOCHE, A., RIVOIR, J., HILLIGES, K. D., (2002), Test Economics for Multi-Site Test with Modern Cost Reduction Techniques, Proceedings of the 20th IEEE VLSI Test Symposium (VTS’02).
56. • VOLKERINK, E. H., KHOCHE, A., RIVOIR, J., HILLIGES, K. D., (2003), Modern Test Techniques: Tradeoffs, Synergies and Scalable Benefits, Journal of Electronics Testing: Theory and Applications, 19, 125 – 135.
57. • WILLIAMS, D., AMBLER, A. P., (2002), System Manufacturing Test Cost Model, Proceedings of the IEEE International Test Conference, 482 – 490.
58. • WILSON, S., FLOOD, B., GOYAL, S., MOSHER, J., BERGIN, S., O’BRIEN, J., KENNEDY, R., (2007), Parameter Estimation for a Model With Both Imperfect Test and Repair, Proceedings of 25th IEEE VLSI Symposium (VTS’07).
59. • WILSON, S., GOYAL, S., (2007), Bayesian Estimation for an Imperfect Test and Repair Model, 12th IEEE European Test Symposium.
60. • WILSON, S., GOYAL, S., (2012), Estimating Production Test Properties from Test Measurement Data, Applied Stochastic Models in Business and Industry, 28, 542 – 557.
61. • ZAKLOUTA, H., (2011), Cost of Quality Tradeoffs in Manufacturing Process and Inspection Stratgy Selection, Yayınlanmamış Yüksek Lisans Tez Çalışması, Massachusetts Institute of Technology, Massachusetts, ABD.
62. • ŽUŽEK, A., BIASIZZO, A., NOVAK, F., (2000), Sequential Diagnosis Tool, Microprocessors and Microsystems, 24, 191 – 197.