An Implementation of Linear Regression using IP-Core and FPGA-based Microcomputer Architecture

Year 2021, Volume: 17 Issue: 2, 53 - 62, 31.12.2021

Abdelkader Lazzem Halit Öztekin Souad Cheurfı

Abstract

To generate more accurate results, machine learning approaches, particularly those based on neural networks, require the usage of accurate real values. Linear regression is a machine learning technique that is commonly used to identify the linear function that best fits a set of data. Due to current trends in systems need and the availability of Field-Programmable Gate Array (FPGA), floating-point implementations are becoming more widespread, and engineers are increasingly using FPGAs as a platform for floating-point implementations. In this paper, to demonstrate the FPGA-based half-precision floating-point (FPU-16) implementation .Two different ways for implementing linear regression are proposed. the first method is by using the assembler of BZK.SAU.FPGA-based microcomputer architecture. The second method is by using IP-Core of Xilinx simulated and tested using Vivado Design Suite software. After implementing both ways we have calculated the mean square error MSE between them and found the result is 7.8×10^(-4).

Keywords

Artificial Neural Network (AAN), Machine Learning (ML), Half-precision Floating-point, Linear Regression, Field-programmable gate array (FPGA), Assembler.

References

• TALIB, Manar Abu, MAJZOUB, Sohaib, NASIR, Qassim, et al. A systematic literature review on hardware implementation of artificial intelligence algorithms. The Journal of Supercomputing, 2021, vol. 77, p. 1897-1938. PURNIMA, Shrivastava, MUKESH, Tiwari, JAIKARAN, Singh, et al. VHDL Environment for Floating point Arithmetic Logic Unit-ALU Design and Simulation. Research Journal of Engineering Sciences. ISSN, 2012, vol. 2278, p. 9472.
• GUMBER, Karan et THANGJAM, Sharmelee. Performance analysis of floating point adder using vhdl on reconfigurable hardware. International Journal of Computer Applications, 2012, vol. 46, no 9, p. 1-5.
• IEEE Standard for Floating-Point Arithmetic," in IEEE Std 754-2019 (Revision of IEEE 754-2008) , vol., no., pp.1-84, 22 July 2019, doi: 10.1109/IEEESTD.2019.8766229.
• DE ASSIS PEDROBON FERREIRA, Willian, GROUT, Ian, et DA SILVA, Alexandre César Rodrigues. FPGA hardware linear regression implementation using fixed-point arithmetic. In: Proceedings of the 32nd Symposium on Integrated . H. Öztekin , A. Gülbağ and F. Temurtaş , "Assembler Design for BZK.SAU.FPGA Micro Computer Architecture", Electronic Letters on Science and Engineering, vol. 13, no. 1, pp. 1-9, Jul. 2017]
• H. Oztekin, F. Temurtas and A. Gulbag, "BZK.SAU.FPGA10.0: Microprocessor architecture design on reconfigurable hardware as an educational tool," 2011 IEEE Symposium on Computers & Informatics, 2011, pp. 385-389.
• Kavitha S, Varuna S and Ramya R, "A comparative analysis on linear regression and support vector regression," 2016 Online International Conference on Green Engineering and Technologies (IC-GET), 2016, pp. 1-5, doi: 10.1109/GET.2016.7916627.
• H. Oztekin, F. Temurtas and A. Gulbag, "BZK.SAU: Implementing a hardware and software-based Computer Architecture simulator for educational purpose," 2010 International Conference On Computer Design and Applications, 2010, pp. V4-90-V4-97.
• Oztekin, Halit; Temurtas, Feyzullah; Gulbag, Ali (2018). On the improvement of the teaching quality and learning effectiveness in the computer organization course through FPGA and modular centered microcomputer design. Computer Applications in Engineering Education,
• D. C. Montgomery, E. A. Peck, and G. G. Vining, Introduction to Linear Regression Analysis (4th ed.). Wiley & Sons, 2006.