FPGA prototipleme: RISC-V tabanlı SoC için çip üstü hata ayıklama modülü ve Raspberry Pi ile OpenOCD JTAG üzerinden test süreçleri

Abstract

Bu çalışma, RISC-V tabanlı bir System-on-Chip (SoC) tasarımının FPGA üzerinde prototipleme sürecini ve bu süreçte entegre edilen çip üstü hata ayıklama modülünü ele almaktadır. FPGA prototipleme, sayısal tasarımların donanım seviyesinde değerlendirilmesi amacıyla FPGA üzerinde uygulanması ve test edilmesi sürecidir. Çalışmada, Raspberry Pi ve OpenOCD kullanılarak JTAG aracılığıyla gerçekleştirilen hata ayıklama işlemleri, SoC'nin çeşitli fonksiyonlarını ve performansını etkin bir şekilde test etmek için kritik bir adım olarak vurgulanmaktadır. Bu yaklaşım, geliştirme sürecinde maliyetleri düşürmeye ve pazara sunma süresini kısaltmaya katkıda bulunurken, tasarımın son silikon versiyonuna geçişte karşılaşılacak riskleri azaltmaktadır. SoC tasarımı, FPGA üzerinde çalıştırılarak fonksiyonel doğrulama kapsamında çeşitli testlere tabi tutulmuş ve başarılı sonuçlar elde edilmiştir. Fonksiyonel doğrulama, bir sayısal tasarımın beklenen davranışları sergileyip sergilemediğini kontrol etmek için uygulanan kritik bir test aşamasıdır. Kayan nokta birimi testi kapsamında sinüs fonksiyonu uygulanarak sinüs değerleri hesaplanmış ve birimin doğru çalıştığı doğrulanmıştır. I2C çevre birimi testinde, bir sensör bağlanarak sensörden elde edilen verilerin doğru şekilde alındığı ve işlendiği tespit edilmiştir. Bit manipulation testi, RISC-V bit manipülasyon komutlarının doğru çalıştığını göstermiştir. FreeRTOS uygulamasında, görev zamanlaması, kesmeler ve kaynak yönetimi başarıyla gerçekleştirilmiş ve sistemin çoklu görev yürütme sırasında hatasız çalıştığı doğrulanmıştır. Atomik işlemler ile CSR (Control and Status Registers) birimlerinin doğru işleyişi değerlendirilmiş ve beklendiği gibi çalıştığı doğrulanmıştır. Bunun yanı sıra, işlemcinin performansı CoreMark ve Dhrystone kıyaslamaları kullanılarak değerlendirilmiştir. CoreMark testinde işlemci, 41.97 iterasyon/saniye (600 iterasyon) skoruna ulaşmış ve CoreMark/MHz değeri 2.51 olarak hesaplanmıştır. Dhrystone kıyaslamasında ise işlemci, 70,582 Dhrystone/saniye performans sergilemiştir. Her bir bileşenin implementasyonu ve ilgili test tezgâhları Verilog HDL ile yazılmış olup, tasarım Terasic De10-Lite FPGA üzerinde uygulanmıştır.

Keywords

• RISC-V İşlemci
• FPGA
• Hata Ayıklama
• Çip üstü Sistem

FPGA prototyping: On-chip debug module for RISC-V based SoC and testing processes using Raspberry Pi with OpenOCD over JTAG

Abstract

This paper presents the FPGA prototyping process of a RISC-V based System-on-Chip (SoC) design and the on-chip debug module integrated in this process. FPGA prototyping is the process of implementing and testing digital designs on an FPGA for hardware-level evaluation. In the study, debugging operations performed via JTAG using Raspberry Pi and OpenOCD are highlighted as a critical step to effectively test the various functions and performance of the SoC. This approach contributes to reducing costs in the development process and shortening time-to-market, while reducing the risks involved in the transition to the final silicon version of the design. The SoC design was executed on FPGA and subjected to various tests within the scope of functional verification and successful results were obtained. Functional verification is a critical testing phase to check whether a digital design exhibits the expected behavior. Within the scope of the floating-point unit test, sine values were calculated by applying the sine function and the correct operation of the unit was verified. In the I2C peripheral test, a sensor was connected, and it was determined that the data obtained from the sensor was received and processed correctly. The bit manipulation test showed that the RISC-V bit manipulation instructions worked correctly. In the FreeRTOS implementation, task scheduling, interrupts, and resource management were successfully implemented, and the system was verified to be error-free during multitasking. The correct operation of atomic operations and CSR (Control and Status Registers) was evaluated and verified to work as expected. In addition, the performance of the processor was evaluated using CoreMark and Dhrystone benchmarks. In the CoreMark test, the processor achieved a score of 41.97 iterations/second (600 iterations) and the CoreMark/MHz value was calculated as 2.51. In the Dhrystone benchmark, the processor performed 70.582 Dhrystones/second. The implementation of each component and the corresponding testbenches were written in Verilog HDL and the design was implemented on a Terasic De10-Lite FPGA.

Keywords

• RISC-V Processor
• FPGA
• Debug
• System on Chip

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