FPGA prototipleme: RISC-V tabanlı SoC için çip üstü hata ayıklama modülü ve Raspberry Pi ile OpenOCD JTAG üzerinden test süreçleri

Öz

Bu çalışma, RISC-V tabanlı bir System-on-Chip (SoC) tasarımının FPGA üzerinde prototipleme sürecini ve bu süreçte entegre edilen çip üstü hata ayıklama modülünü ele almaktadır. FPGA prototipleme, sayısal tasarımların donanım seviyesinde değerlendirilmesi amacıyla FPGA üzerinde uygulanması ve test edilmesi sürecidir. Çalışmada, Raspberry Pi ve OpenOCD kullanılarak JTAG aracılığıyla gerçekleştirilen hata ayıklama işlemleri, SoC'nin çeşitli fonksiyonlarını ve performansını etkin bir şekilde test etmek için kritik bir adım olarak vurgulanmaktadır. Bu yaklaşım, geliştirme sürecinde maliyetleri düşürmeye ve pazara sunma süresini kısaltmaya katkıda bulunurken, tasarımın son silikon versiyonuna geçişte karşılaşılacak riskleri azaltmaktadır. SoC tasarımı, FPGA üzerinde çalıştırılarak fonksiyonel doğrulama kapsamında çeşitli testlere tabi tutulmuş ve başarılı sonuçlar elde edilmiştir. Fonksiyonel doğrulama, bir sayısal tasarımın beklenen davranışları sergileyip sergilemediğini kontrol etmek için uygulanan kritik bir test aşamasıdır. Kayan nokta birimi testi kapsamında sinüs fonksiyonu uygulanarak sinüs değerleri hesaplanmış ve birimin doğru çalıştığı doğrulanmıştır. I2C çevre birimi testinde, bir sensör bağlanarak sensörden elde edilen verilerin doğru şekilde alındığı ve işlendiği tespit edilmiştir. Bit manipulation testi, RISC-V bit manipülasyon komutlarının doğru çalıştığını göstermiştir. FreeRTOS uygulamasında, görev zamanlaması, kesmeler ve kaynak yönetimi başarıyla gerçekleştirilmiş ve sistemin çoklu görev yürütme sırasında hatasız çalıştığı doğrulanmıştır. Atomik işlemler ile CSR (Control and Status Registers) birimlerinin doğru işleyişi değerlendirilmiş ve beklendiği gibi çalıştığı doğrulanmıştır. Bunun yanı sıra, işlemcinin performansı CoreMark ve Dhrystone kıyaslamaları kullanılarak değerlendirilmiştir. CoreMark testinde işlemci, 41.97 iterasyon/saniye (600 iterasyon) skoruna ulaşmış ve CoreMark/MHz değeri 2.51 olarak hesaplanmıştır. Dhrystone kıyaslamasında ise işlemci, 70,582 Dhrystone/saniye performans sergilemiştir. Her bir bileşenin implementasyonu ve ilgili test tezgâhları Verilog HDL ile yazılmış olup, tasarım Terasic De10-Lite FPGA üzerinde uygulanmıştır.

Anahtar Kelimeler

• RISC-V İşlemci
• FPGA
• Hata Ayıklama
• Çip üstü Sistem

FPGA prototyping: On-chip debug module for RISC-V based SoC and testing processes using Raspberry Pi with OpenOCD over JTAG

Öz

This paper presents the FPGA prototyping process of a RISC-V based System-on-Chip (SoC) design and the on-chip debug module integrated in this process. FPGA prototyping is the process of implementing and testing digital designs on an FPGA for hardware-level evaluation. In the study, debugging operations performed via JTAG using Raspberry Pi and OpenOCD are highlighted as a critical step to effectively test the various functions and performance of the SoC. This approach contributes to reducing costs in the development process and shortening time-to-market, while reducing the risks involved in the transition to the final silicon version of the design. The SoC design was executed on FPGA and subjected to various tests within the scope of functional verification and successful results were obtained. Functional verification is a critical testing phase to check whether a digital design exhibits the expected behavior. Within the scope of the floating-point unit test, sine values were calculated by applying the sine function and the correct operation of the unit was verified. In the I2C peripheral test, a sensor was connected, and it was determined that the data obtained from the sensor was received and processed correctly. The bit manipulation test showed that the RISC-V bit manipulation instructions worked correctly. In the FreeRTOS implementation, task scheduling, interrupts, and resource management were successfully implemented, and the system was verified to be error-free during multitasking. The correct operation of atomic operations and CSR (Control and Status Registers) was evaluated and verified to work as expected. In addition, the performance of the processor was evaluated using CoreMark and Dhrystone benchmarks. In the CoreMark test, the processor achieved a score of 41.97 iterations/second (600 iterations) and the CoreMark/MHz value was calculated as 2.51. In the Dhrystone benchmark, the processor performed 70.582 Dhrystones/second. The implementation of each component and the corresponding testbenches were written in Verilog HDL and the design was implemented on a Terasic De10-Lite FPGA.

Anahtar Kelimeler

• RISC-V Processor
• FPGA
• Debug
• System on Chip

Kaynakça

1. [1] Farooq U, Mehrez H. “Pre-Silicon verification using multi-FPGA platforms: a review”. Journal of Electron Testing, 37(1), 7–24, 2021.
2. [2] Korkmaz N. “Fitzhugh-Nagumo nöron modelinin rotasyon-geçiş prosedürü ve donanım doğrulaması”. Pamukkale Üniversitesi Mühendislik Bilimleri Dergisi, 24(3), 316–323, 2024.
3. [3] Zang Z, Liu Y, Cheung RCC. “Reconfigurable RISC-V secure processor and SoC integration”. 2019 IEEE International Conference on Industrial Technology (ICIT), Melbourne, Australia, 13–15 February 2019.
4. [4] University of California, Berkeley. “RISC-V Project”. https://riscv.org/about/history/ (07.01.2024).
5. [5] Cui E, Li T, Wei Q. “RISC-V ınstruction set architecture extensions: a survey”. IEEE Access, 11, 24696–24711, 2023.
6. [6] RISC-V Foundation. “RISC-V ISA Manual”. https://github.com/riscv/riscv-isa-manual (12.01.2025).
7. [7] Singh A, Kumar A, Singh A, Anirudh R, Pushpalatha KN. “Design and implementation of RISC-V ISA (RV32IM) on FPGA”. International Journal of VLSI & Signal Processing, 10, 17–21, 2023.
8. [8] Wang X, Zhou L, Li Y, Zhang P, Lin H, Xu J. “xBGAS: a global address space extension on RISC-V for high performance computing”. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), Portland, OR, USA, 28 June 2021.

9. [9] Chen J, Li D, Mi Z, Liu Y, Zang B, Guan H, Chen H. “Du-visor: a user-level hypervisor through delegated virtualization”. https://github.com/IPADS-DuVisor/DuVisor (02.10.2025).
10. [10] Tine B, Yalamarthy KP, Elsabbagh F, Kim H. “Vortex: extending the RISC-V ISA for GPGPU and 3D-Graphics”. 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO ’21), Athens, Greece, 17–21 October 2021.
11. [11] RISC-V International. “RISC-V Debug Specification”. https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf (07.01.2024).
12. [12] Poli L, Saha S, Zhai X, Mcdonald-Maier KD. “Design and Implementation of a RISC-V Processor on FPGA”. 2021 17th International Conference on Mobility, Sensing and Networking (MSN), Exeter, United Kingdom, 13–15 December 2021.
13. [13] Pilavendiran SA, Keshavarajan JL, Vijayakumar S. “Design and development of JTAG using raspberry pi”. International Journal of Engineering Applied Sciences and Technology, 4, 75–79, 2020.
14. [14] Rico-García P, Yañez-Vargas JI, Parra-Michel R, Conde-Almada E. “Debugging and programming a RISC-V processor using the IEEE 1149.1 standard”. Journal of Applied Computing, 7(21), 1–9, 2023.
15. [15] Salehi M, Degani L, Roveri M, Hughes D, Crispo B. “Discovery and Identification of Memory Corruption Vulnerabilities on Bare-Metal Embedded Devices”. IEEE Transactions on Dependable and Secure Computing, 20(2), 1124–1138, 2023.
16. [16] OpenOCD. “Open On-Chip Debugger”. https://openocd.org/doc/pdf/openocd.pdf (20.01.2024).
17. [17] Gao S, Wu D, Xiao W, Wang Z, Yang Z, Gao W. “A novel method for on-chip debugging based on RISC-V processor”. MATEC Web of Conferences, 355, 03055, 2022.
18. [18] Toker O. “A high-level synthesis approach for a RISC-V RV32I-Based system on chip and its FPGA implementation”. Engineering Proceedings, 58(1), 72, 2023.
19. [19] Heinz C, Lavan Y, Hofmann J, Koch A. “A catalog and ın-hardware evaluation of open-source drop-in compatible RISC-V Softcore Processors”. 2019 International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, 9–11 December 2019.
20. [20] Elsadek I, Tawfik EY. “RISC-V resource-constrained cores: a survey and energy comparison”. 19th IEEE International New Circuits and Systems Conference, Toulon, France, 13–16 June 2021.
21. [21] EEMBC (Embedded Microprocessor Benchmark Consortium). “CoreMark Benchmark”. www.eembc.org (15.01.2025).
22. [22] Kreier R. “CoreMark Benchmarking Overview”. https://kreier.github.io/benchmark/CoreMark/ (15.03.2025).
23. [23] Weicker R. “Dhrystone: a synthetic benchmark”. Communications of the ACM, 27(10), 1013–1030, 1984.
24. [24] Mo W, Liu J, Wang Y, Yan F, Xiong B, Guan J. “An SDPF RISC-V processor with 55.9% dhrystone ımprovement using two-stage pseudo-pipelined architecture for IoT applications”. International Journal of Circuit Theory and Applications, 2025. https://doi.org/10.1002/cta.4514
25. [25] Bora S, Paily R. “A high-performance core micro-architecture based on RISC-V ISA for low power applications”. IEEE Transactions on Circuits and Systems II: Express Briefs, 68(6), 2132–2136, 2021.
26. [26] ORCA. “A RISC-V Processor for FPGA Evaluation. GitHub Repository”. https://github.com/riscveval/orca-1 (15.03.2025).
27. [27] PicoRV32. “A Size-Optimized RISC-V CPU Core. GitHub Repository”. https://github.com/YosysHQ/picorv32 (15.03.2025).
28. [28] mmRISC-1. “A Minimal RISC-V CPU Implementation. GitHub Repository”. https://github.com/munetomo-maruyama/mmRISC-1 (01.01.2024).