Custom TTA Operations for Accelerating the Ascon Encryption Algorithm
Öz
Anahtar Kelimeler
Kaynakça
- [1] W. J. Buchanan, S. Li, and R. Asif, “Lightweight cryptography methods,” J. Cyber Secur. Technol., vol. 1, no. 3–4, pp. 187–201, 2017. https://doi.org/10.1080/23742917.2017.1384917
- [2] K. Mohajerani, L. Beckwith, A. Abdulgadir, J.-P. Kaps, and K. Gaj, “Lightweight champions of the world: Side-channel resistant open hardware for finalists in the NIST Lightweight Cryptography Standardization Process,” ACM Trans. Embed. Comput. Syst., 2024. https://doi.org/10.1145/3677320
- [3] Sonmez Turan M, McKay K, Chang D, Bassham LE, Kang J, Waller ND, Kelsey JM, Hong D, “Status Report on the Final Round of the NIST Lightweight Cryptography Standardization Process,” (National Institute of Standards and Technology, Gaithersburg, MD), NIST Interagency or Internal Report (IR) NIST IR 8454., 2023. https://doi.org/10.6028/NIST.IR.8454.
- [4] C. Dobraunig, M. Eichlseder, F. Mendel, and M. Schläffer, “Ascon v1.2: Lightweight authenticated encryption and hashing” J. Cryptology, vol. 34, no. 3, 2021. https://doi.org/10.1007/s00145-021-09398-9
- [5] C. Shekhar, Raj Singh, A. S. Mandal, S. C. Bose, R. Saini and P. Tanwar, "Application Specific Instruction Set Processors: redefining hardware-software boundary," 17th International Conference on VLSI Design. Proceedings., Mumbai, India, 2004, pp. 915-918, doi: 10.1109/ICVD.2004.1261047.
- [6] H. Corporaal and M. Arnold, “Using transport triggered architectures for embedded processor design,” Integr. Comput. Aided Eng., vol. 5, no. 1, pp. 19–38, 1998. doi: 10.3233/ICA-1998-5103
- [7] P. Hamalainen, J. Heikkinen, M. Hannikainen and T. D. Hamalainen, "Design of transport triggered architecture processors for wireless encryption," 8th Euromicro Conference on Digital System Design (DSD'05), Porto, Portugal, 2005, pp. 144-152, doi: 10.1109/DSD.2005.33.
- [8] P. Hamalainen, M. Hannikainen, T. Hamalainen, H. Corporaal and J. Saarvinen, "Implementation of encryption algorithms on transport triggered architectures," ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), Sydney, NSW, Australia, 2001, pp. 726-729 vol. 4, doi: 10.1109/ISCAS.2001.922340.
Ayrıntılar
Birincil Dil
İngilizce
Konular
Dijital İşlemci Mimarileri, Gömülü Sistemler, Sayısal Tasarım
Bölüm
Araştırma Makalesi
Yazarlar
Latif Akçay
*
0000-0003-2580-2643
Türkiye
Yayımlanma Tarihi
31 Aralık 2024
Gönderilme Tarihi
11 Kasım 2024
Kabul Tarihi
9 Aralık 2024
Yayımlandığı Sayı
Yıl 2024 Cilt: 7 Sayı: 2